{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:08:18Z","timestamp":1781885298698,"version":"3.54.5"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,2]]},"DOI":"10.1109\/isscc.2009.4977473","type":"proceedings-article","created":{"date-parts":[[2009,6,3]],"date-time":"2009-06-03T13:51:36Z","timestamp":1244037096000},"page":"392-393,393a","source":"Crossref","is-referenced-by-count":9,"title":["A 2.2GHz 7.6mW sub-sampling PLL with &amp;#x2212;126dBc\/Hz in-band phase noise and 0.15psrms jitter in 0.18&amp;#x00B5;m CMOS"],"prefix":"10.1109","author":[{"family":"Xiang Gao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"E.A.M.","family":"Klumperink","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Bohsali","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"B.","family":"Nauta","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"3","author":"crawford","year":"1994","journal-title":"Frequency Synthesizer Design Handbook Artech House"},{"key":"2","article-title":"jitter analysis and a benchmarking figure-of-merit for phase-locked loops","author":"gao","year":"0","journal-title":"IEEE Trans Circuits and Systems-II"},{"key":"1","author":"vaucher","year":"2002","journal-title":"Architectures for RF Frequency Synthesizers"},{"key":"7","author":"banerjee","year":"2008","journal-title":"PLL Performance Simulation and Design 4th Edition"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"5","first-page":"594","article-title":"a 6.25ghz 1v lc-pll in 0.13m cmos","author":"gu","year":"2006","journal-title":"ISSCC Dig Tech Papers"},{"key":"4","first-page":"178","article-title":"a 2.5 to 10 ghz clock multiplier unit with 0.22ps rms jitter in a 0.18m cmos technology","author":"van de beek","year":"2003","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2009 IEEE International Solid-State Circuits Conference (ISSCC 2009)","location":"San Francisco, CA","start":{"date-parts":[[2009,2,8]]},"end":{"date-parts":[[2009,2,12]]}},"container-title":["2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4926119\/4977283\/04977473.pdf?arnumber=4977473","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T15:54:24Z","timestamp":1489766064000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4977473\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,2]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/isscc.2009.4977473","relation":{},"subject":[],"published":{"date-parts":[[2009,2]]}}}