{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,6]],"date-time":"2026-09-06T02:00:50Z","timestamp":1788660050951,"version":"build-2803163510"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,2]]},"DOI":"10.1109\/isscc.2010.5433818","type":"proceedings-article","created":{"date-parts":[[2010,3,24]],"date-time":"2010-03-24T10:35:14Z","timestamp":1269426914000},"page":"350-351","source":"Crossref","is-referenced-by-count":10,"title":["A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS"],"prefix":"10.1109","author":[{"given":"Masood","family":"Qazi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kevin","family":"Stawiasz","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Leland","family":"Chang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Anantha","family":"Chandrakasan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"226","article-title":"The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-$0.18\\mu{\\rm m}$ Technologies","author":"zhang","year":"2000","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342739"},{"key":"ref10","first-page":"456","article-title":"A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in 32nm High-k Metal-Gate CMOS with Integrated Power Management","author":"wang","year":"2008","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320819"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523216"},{"key":"ref8","first-page":"29","article-title":"Canary Replica Feedback for Near-DRV Standby ${\\rm V}_{{\\rm DD}}$ Scaling in a 90nm SRAM","author":"wang","year":"2007","journal-title":"CICC Dig Tech Papers"},{"key":"ref7","first-page":"253","article-title":"A Fully Synchronized, Pipelined, and Re-Configurable 50Mb SRAM on 90nm CMOS Technology for Logic Application","author":"zhang","year":"2003","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref2","first-page":"315","article-title":"High-performance, Low-power, and Leakage-toler-ance Challenges for SUb-70nm Microprocessor Circuits","author":"krishnamurthy","year":"2002","journal-title":"ESSCIRC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0419"},{"key":"ref9","first-page":"55","article-title":"SRAM Leakage Suppression by Minimizing Standby Supply Voltage","author":"din","year":"2004","journal-title":"Symp ISQED Dig Tech Papers"}],"event":{"name":"2010 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2010,2,7]]},"end":{"date-parts":[[2010,2,11]]}},"container-title":["2010 IEEE International Solid-State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5428240\/5433812\/05433818.pdf?arnumber=5433818","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T15:31:11Z","timestamp":1489851071000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5433818\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/isscc.2010.5433818","relation":{},"subject":[],"published":{"date-parts":[[2010,2]]}}}