{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,26]],"date-time":"2025-07-26T09:13:33Z","timestamp":1753521213589},"reference-count":3,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,2]]},"DOI":"10.1109\/isscc.2010.5433903","type":"proceedings-article","created":{"date-parts":[[2010,3,24]],"date-time":"2010-03-24T14:35:14Z","timestamp":1269441314000},"page":"328-329","source":"Crossref","is-referenced-by-count":17,"title":["A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP\/media accelerators in 32nm CMOS"],"prefix":"10.1109","author":[{"given":"Amit","family":"Agarwal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanu K","family":"Mathew","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven K","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark A","family":"Anders","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Himanshu","family":"Kaul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Farhana","family":"Sheikh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajaraman","family":"Ramanarayanan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suresh","family":"Srinivasan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ram","family":"Krishnamurthy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shekhar","family":"Borkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332709"},{"key":"ref2","first-page":"50","article-title":"A 1GOPS Reconfigurable Signal Processing IC with Embedded FPGA and 3-port 1.2GB\/s Flash Memory Subsystem","author":"borgatti","year":"2003","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","article-title":"A 32nm Logic Technology Featuring 2nd Generation High-K + Metal Gate Transistors, Enhanced Channel Strain and $0.171\\mu{\\rm m}^{2}$ SRAM Cell Size in a 291 Mb Array","author":"natarajan","year":"2008","journal-title":"IEDM Tech Dig paper 27 9"}],"event":{"name":"2010 IEEE International Solid- State Circuits Conference - (ISSCC)","start":{"date-parts":[[2010,2,7]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2010,2,11]]}},"container-title":["2010 IEEE International Solid-State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5428240\/5433812\/05433903.pdf?arnumber=5433903","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T19:35:30Z","timestamp":1489865730000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5433903\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/isscc.2010.5433903","relation":{},"subject":[],"published":{"date-parts":[[2010,2]]}}}