{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,28]],"date-time":"2025-06-28T07:22:52Z","timestamp":1751095372361,"version":"3.28.0"},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,2]]},"DOI":"10.1109\/isscc.2011.5746285","type":"proceedings-article","created":{"date-parts":[[2011,4,8]],"date-time":"2011-04-08T23:44:40Z","timestamp":1302306280000},"page":"208-210","source":"Crossref","is-referenced-by-count":8,"title":["A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS"],"prefix":"10.1109","author":[{"given":"Masood","family":"Qazi","sequence":"first","affiliation":[]},{"given":"Michael","family":"Clinton","sequence":"additional","affiliation":[]},{"given":"Steven","family":"Bartling","sequence":"additional","affiliation":[]},{"given":"Anantha P.","family":"Chandrakasan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"50","article-title":"A 0.9 V1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure","author":"yamaoka","year":"2004","journal-title":"ISSCC Digest Tech Papers"},{"key":"ref3","first-page":"535","article-title":"Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu\/FSG logic process","author":"moise","year":"2002","journal-title":"IEDM Tech Digest"},{"key":"ref2","first-page":"38","article-title":"A nonvolatile ferroelectric RAM with common plate folded bit-line cell and enhanced data sensing scheme","volume":"426","author":"jeon","year":"2001","journal-title":"ISSCC Digest Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433950"}],"event":{"name":"2011 IEEE International Solid- State Circuits Conference - (ISSCC)","start":{"date-parts":[[2011,2,20]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2011,2,24]]}},"container-title":["2011 IEEE International Solid-State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5740653\/5746170\/05746285.pdf?arnumber=5746285","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T07:09:30Z","timestamp":1490080170000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5746285\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,2]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isscc.2011.5746285","relation":{},"subject":[],"published":{"date-parts":[[2011,2]]}}}