{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T09:00:59Z","timestamp":1767085259765},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1109\/isscc.2012.6176871","type":"proceedings-article","created":{"date-parts":[[2012,4,5]],"date-time":"2012-04-05T17:40:15Z","timestamp":1333647615000},"page":"44-46","source":"Crossref","is-referenced-by-count":15,"title":["A 1.2V 30nm 1.6Gb\/s\/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme"],"prefix":"10.1109","author":[{"given":"Yong-Cheol","family":"Bae","sequence":"first","affiliation":[]},{"given":"Joon-Young","family":"Park","sequence":"additional","affiliation":[]},{"given":"Sang Jae","family":"Rhee","sequence":"additional","affiliation":[]},{"given":"Seung Bum","family":"Ko","sequence":"additional","affiliation":[]},{"given":"Yonggwon","family":"Jeong","sequence":"additional","affiliation":[]},{"given":"Kwang-Sook","family":"Noh","sequence":"additional","affiliation":[]},{"given":"Younghoon","family":"Son","sequence":"additional","affiliation":[]},{"given":"Jaeyoun","family":"Youn","sequence":"additional","affiliation":[]},{"given":"Yonggyu","family":"Chu","sequence":"additional","affiliation":[]},{"given":"Hyunyoon","family":"Cho","sequence":"additional","affiliation":[]},{"given":"Mijo","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Daesik","family":"Yim","sequence":"additional","affiliation":[]},{"given":"Hyo-Chang","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Sang-Hoon","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Hye-In","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Sungmin","family":"Yim","sequence":"additional","affiliation":[]},{"given":"Jung-Bae","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Joo Sun","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Kyungseok","family":"Oh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"JEDEC Standard DDR3 SDRAM Specification","year":"2010","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.67"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746413"},{"key":"4","first-page":"314","article-title":"A 1.2Gb\/s\/pin Double Data Rate SDRAM with On-Die-Termination","author":"song","year":"2003","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2012 IEEE International Solid- State Circuits Conference - (ISSCC)","start":{"date-parts":[[2012,2,19]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2012,2,23]]}},"container-title":["2012 IEEE International Solid-State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6171933\/6176863\/06176871.pdf?arnumber=6176871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T19:26:16Z","timestamp":1490124376000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6176871\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isscc.2012.6176871","relation":{},"subject":[],"published":{"date-parts":[[2012,2]]}}}