{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:33:45Z","timestamp":1771698825541,"version":"3.50.1"},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1109\/isscc.2012.6176990","type":"proceedings-article","created":{"date-parts":[[2012,4,5]],"date-time":"2012-04-05T17:40:15Z","timestamp":1333647615000},"page":"234-236","source":"Crossref","is-referenced-by-count":13,"title":["Capacitive-coupling wordline boosting with self-induced V<inf>CC<\/inf> collapse for write V<inf>MIN<\/inf> reduction in 22-nm 8T SRAM"],"prefix":"10.1109","author":[{"given":"Jaydeep","family":"Kulkarni","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bibiche","family":"Geuskens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tanay","family":"Karnik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muhammad","family":"Khellah","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Tschanz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585947"},{"key":"2","first-page":"352","article-title":"PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction","author":"raychowdhury","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"1","first-page":"58","article-title":"A family of 45nm IA processors","author":"kumar","year":"2009","journal-title":"ISSCC Dig Tech Papers"},{"key":"4","first-page":"264","article-title":"A fully integrated multi-CPU, GPU and memory controller 32nm processor","author":"yuffe","year":"2011","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2012 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2012,2,19]]},"end":{"date-parts":[[2012,2,23]]}},"container-title":["2012 IEEE International Solid-State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6171933\/6176863\/06176990.pdf?arnumber=6176990","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T19:13:45Z","timestamp":1490123625000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6176990\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isscc.2012.6176990","relation":{},"subject":[],"published":{"date-parts":[[2012,2]]}}}