{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:41:55Z","timestamp":1773247315921,"version":"3.50.1"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2012,2,1]],"date-time":"2012-02-01T00:00:00Z","timestamp":1328054400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2012,2,1]],"date-time":"2012-02-01T00:00:00Z","timestamp":1328054400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1109\/isscc.2012.6177075","type":"proceedings-article","created":{"date-parts":[[2012,4,5]],"date-time":"2012-04-05T13:40:15Z","timestamp":1333633215000},"page":"426-428","source":"Crossref","is-referenced-by-count":40,"title":["6.4Gb\/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers"],"prefix":"10.1109","author":[{"given":"Youngjoo","family":"Lee","sequence":"first","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hoyoung","family":"Yoo","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Injae","family":"Yoo","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"In-Cheol","family":"Park","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","first-page":"202","article-title":"A 32Gb MLC NAND Flash Memory with Vth Margin-Expanding Scheme in 26nm CMOS","author":"kim","year":"2011","journal-title":"ISSCC Dig Tech Papers"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746283"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.63"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2158709"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2065630"},{"key":"4","first-page":"497","article-title":"A 4Gb 2b\/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB\/s System Read Throughput","author":"micheloni","year":"2006","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2012 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2012,2,19]]},"end":{"date-parts":[[2012,2,23]]}},"container-title":["2012 IEEE International Solid-State Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6171933\/6176863\/06177075.pdf?arnumber=6177075","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:13:13Z","timestamp":1755907993000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6177075\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2012.6177075","relation":{},"subject":[],"published":{"date-parts":[[2012,2]]}}}