{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:58:25Z","timestamp":1759147105284},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,2]]},"DOI":"10.1109\/isscc.2013.6487696","type":"proceedings-article","created":{"date-parts":[[2013,4,5]],"date-time":"2013-04-05T16:58:31Z","timestamp":1365181111000},"page":"194-195","source":"Crossref","is-referenced-by-count":43,"title":["Nonvolatile logic-in-memory array processor in 90nm MTJ\/MOS achieving 75% leakage reduction using cycle-based power gating"],"prefix":"10.1109","author":[{"given":"M.","family":"Natsui","sequence":"first","affiliation":[]},{"given":"D.","family":"Suzuki","sequence":"additional","affiliation":[]},{"given":"N.","family":"Sakimura","sequence":"additional","affiliation":[]},{"given":"R.","family":"Nebashi","sequence":"additional","affiliation":[]},{"given":"Y.","family":"Tsuji","sequence":"additional","affiliation":[]},{"given":"A.","family":"Morioka","sequence":"additional","affiliation":[]},{"given":"T.","family":"Sugibayashi","sequence":"additional","affiliation":[]},{"given":"S.","family":"Miura","sequence":"additional","affiliation":[]},{"given":"H.","family":"Honjo","sequence":"additional","affiliation":[]},{"given":"K.","family":"Kinoshita","sequence":"additional","affiliation":[]},{"given":"S.","family":"Ikeda","sequence":"additional","affiliation":[]},{"given":"T.","family":"Endoh","sequence":"additional","affiliation":[]},{"given":"H.","family":"Ohno","sequence":"additional","affiliation":[]},{"given":"T.","family":"Hanyu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2172644"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.894617"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1143\/APEX.2.023004"},{"key":"6","first-page":"1971","article-title":"High-speed simulator including accurate mtj models for spintronics integrated circuit design 2012","author":"sakimura","year":"2012","journal-title":"IEEE Int Symp Circuits and Systems"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2011.2133230"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177067"}],"event":{"name":"2013 IEEE International Solid-State Circuits Conference (ISSCC 2013)","start":{"date-parts":[[2013,2,17]]},"location":"San Francisco, CA","end":{"date-parts":[[2013,2,21]]}},"container-title":["2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6480926\/6487590\/06487696.pdf?arnumber=6487696","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T14:47:11Z","timestamp":1490194031000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6487696\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2013.6487696","relation":{},"subject":[],"published":{"date-parts":[[2013,2]]}}}