{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,4]],"date-time":"2025-05-04T16:44:45Z","timestamp":1746377085764},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,2]]},"DOI":"10.1109\/isscc.2013.6487747","type":"proceedings-article","created":{"date-parts":[[2013,4,5]],"date-time":"2013-04-05T16:58:31Z","timestamp":1365181111000},"page":"308-309","source":"Crossref","is-referenced-by-count":3,"title":["A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4&amp;#x00D7;Z&lt;inf&gt;0&lt;\/inf&gt; at both TX and RX"],"prefix":"10.1109","author":[{"family":"Soo-Min Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jong-Hoon Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jongsam Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yunsaing Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hyunbae Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jae-Yoon Sim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hong-June Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","first-page":"348","article-title":"A 1.0625-to-15.025gb\/s multimedia transceiver with fullrate source-series-terminated transmitter driver and floating-tap decision-feedback equalizer in 40nm cmos","author":"quan","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"2","first-page":"136","article-title":"Single-ended transceiver design techniques for 5.33gb\/s graphics applications","author":"partovi","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560300"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373378"},{"key":"4","first-page":"112","article-title":"A 3.2gb\/s 8b single-ended integrating dfe rx for 2-drop dram interface with internal reference voltage and digital calibration","author":"chi","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"}],"event":{"name":"2013 IEEE International Solid-State Circuits Conference (ISSCC 2013)","start":{"date-parts":[[2013,2,17]]},"location":"San Francisco, CA","end":{"date-parts":[[2013,2,21]]}},"container-title":["2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6480926\/6487590\/06487747.pdf?arnumber=6487747","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T14:00:30Z","timestamp":1490191230000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6487747\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2013.6487747","relation":{},"subject":[],"published":{"date-parts":[[2013,2]]}}}