{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,29]],"date-time":"2026-08-29T15:39:12Z","timestamp":1788017952363,"version":"build-2784847793"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/isscc.2014.6757359","type":"proceedings-article","created":{"date-parts":[[2014,3,7]],"date-time":"2014-03-07T22:14:09Z","timestamp":1394230449000},"page":"108-109","source":"Crossref","is-referenced-by-count":16,"title":["5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep"],"prefix":"10.1109","author":[{"given":"Carlos","family":"Tokunaga","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joseph F.","family":"Ryan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Charles","family":"Augustine","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jaydeep P.","family":"Kulkarni","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yi-Chun","family":"Shih","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stephen T.","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rinkle","family":"Jain","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Keith","family":"Bowman","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Arijit","family":"Raychowdhury","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Muhammad M.","family":"Khellah","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"James W.","family":"Tschanz","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746315"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243806"},{"key":"1","first-page":"56","article-title":"A 22nm IA multi-CPU and GPU system-on-chip","author":"damaraju","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6478969"},{"key":"4","article-title":"Dual-vcc 8T bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic range","author":"kulkarni","year":"2013","journal-title":"IEEE Symp VLSI Circuits"}],"event":{"name":"2014 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2014,2,9]]},"end":{"date-parts":[[2014,2,13]]}},"container-title":["2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6747109\/6757318\/06757359.pdf?arnumber=6757359","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:46:55Z","timestamp":1490305615000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6757359\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2014.6757359","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}