{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,30]],"date-time":"2026-04-30T17:01:33Z","timestamp":1777568493725,"version":"3.51.4"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/isscc.2014.6757413","type":"proceedings-article","created":{"date-parts":[[2014,3,7]],"date-time":"2014-03-07T22:14:09Z","timestamp":1394230449000},"page":"232-233","source":"Crossref","is-referenced-by-count":26,"title":["13.2 A 14nm FinFET 128Mb 6T SRAM with V<inf>MIN<\/inf>-enhancement techniques for low-power applications"],"prefix":"10.1109","author":[{"given":"Taejoong","family":"Song","sequence":"first","affiliation":[]},{"given":"Woojin","family":"Rim","sequence":"additional","affiliation":[]},{"given":"Jonghoon","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Giyong","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Jaeho","family":"Park","sequence":"additional","affiliation":[]},{"given":"Sunghyun","family":"Park","sequence":"additional","affiliation":[]},{"given":"Kang-Hyun","family":"Baek","sequence":"additional","affiliation":[]},{"given":"Sanghoon","family":"Baek","sequence":"additional","affiliation":[]},{"given":"Sang-Kyu","family":"Oh","sequence":"additional","affiliation":[]},{"given":"Jinsuk","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Sungbong","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Gyuhong","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jintae","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Youngkeun","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Kee Sup","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Sang-Pil","family":"Sim","sequence":"additional","affiliation":[]},{"given":"Jong Shik","family":"Yoon","sequence":"additional","affiliation":[]},{"given":"Kyu-Myung","family":"Choi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523215"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523214"},{"key":"10","first-page":"316","article-title":"A 20nm 112Mb SRAM in high-metal-gate with assist circuitry for low-leakage and low-VMIN applications","author":"chang","year":"2013","journal-title":"ISSCC Dig Tech Papers"},{"key":"1","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1109\/MCD.2004.1263404","article-title":"Turning silicon on its edge, overcoming silicon scaling barriers with double-gate and finfet technology","volume":"20","author":"nowak","year":"2004","journal-title":"IEEE Circuit and Devices Magazine"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746307"},{"key":"6","first-page":"348","article-title":"A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149?m2 cell in 32nm high-k metal-gate CMOS","author":"fujimura","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977505"},{"key":"4","first-page":"458","article-title":"A process-variation-tolerant dual-power-supply SRAM with 0.179?m 2 cell in 40nm CMOS using level-programmable wordline driver","author":"hirabayashi","year":"2009","journal-title":"ISSCC Dig Tech Papers"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487753"},{"key":"8","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry","author":"karl","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907998"}],"event":{"name":"2014 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2014,2,9]]},"end":{"date-parts":[[2014,2,13]]}},"container-title":["2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6747109\/6757318\/06757413.pdf?arnumber=6757413","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T09:15:13Z","timestamp":1498122913000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6757413\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/isscc.2014.6757413","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}