{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T10:31:09Z","timestamp":1780050669369,"version":"3.53.1"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/isscc.2014.6757414","type":"proceedings-article","created":{"date-parts":[[2014,3,7]],"date-time":"2014-03-07T17:14:09Z","timestamp":1394212449000},"page":"234-235","source":"Crossref","is-referenced-by-count":26,"title":["13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read\/write assists"],"prefix":"10.1109","author":[{"given":"Makoto","family":"Yabuuchi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yasumasa","family":"Tsukamoto","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Masao","family":"Morimoto","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Miki","family":"Tanaka","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Koji","family":"Nii","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746307"},{"key":"2","first-page":"316","article-title":"A 20nm 112Mb SRAM in high-k metal-gate with assist circuitry for low-leakage and low-VMIN applications","author":"chang","year":"2013","journal-title":"ISSCC Dig"},{"key":"1","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry","author":"karl","year":"2012","journal-title":"ISSCC Dig"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164021"},{"key":"4","first-page":"118","article-title":"A 20nm 0.6V 2.1?W\/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme","author":"fujiwara","year":"2013","journal-title":"Symp VLSI Circuits"}],"event":{"name":"2014 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2014,2,9]]},"end":{"date-parts":[[2014,2,13]]}},"container-title":["2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6747109\/6757318\/06757414.pdf?arnumber=6757414","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T17:54:56Z","timestamp":1490291696000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6757414\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2014.6757414","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}