{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T06:55:34Z","timestamp":1769842534123,"version":"3.49.0"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/isscc.2014.6757416","type":"proceedings-article","created":{"date-parts":[[2014,3,7]],"date-time":"2014-03-07T22:14:09Z","timestamp":1394230449000},"page":"238-239","source":"Crossref","is-referenced-by-count":14,"title":["13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V<inf>MIN<\/inf> applications"],"prefix":"10.1109","author":[{"given":"Yen-Huei","family":"Chen","sequence":"first","affiliation":[]},{"given":"Wei-Min","family":"Chan","sequence":"additional","affiliation":[]},{"given":"Wei-Cheng","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Hung-Jen","family":"Liao","sequence":"additional","affiliation":[]},{"given":"Kuo-Hua","family":"Pan","sequence":"additional","affiliation":[]},{"given":"Jhon-Jhy","family":"Liaw","sequence":"additional","affiliation":[]},{"given":"Tang-Hsuan","family":"Chung","sequence":"additional","affiliation":[]},{"given":"Quincy","family":"Li","sequence":"additional","affiliation":[]},{"given":"George H.","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Chih-Yung","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Mu-Chi","family":"Chiang","sequence":"additional","affiliation":[]},{"given":"Shien-Yang","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Sreedhar","family":"Natarajan","sequence":"additional","affiliation":[]},{"given":"Jonathan","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746307"},{"key":"2","first-page":"348","article-title":"A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149?m2 cell in 32nm high-K metal-gate CMOS","author":"fujimura","year":"2010","journal-title":"ISSCC Digest of Technical Papers"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131655"},{"key":"5","first-page":"316","article-title":"A 20nm 112Mb SRAM in high-k metal-gate with assist circuitry for low-leakage and low-vmin applications","author":"chang","year":"2013","journal-title":"ISSCC Digest of Technical Papers"},{"key":"4","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active vmin enhanced assist circuitry","author":"karl","year":"2012","journal-title":"ISSCC Digest of Technical Papers"}],"event":{"name":"2014 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2014,2,9]]},"end":{"date-parts":[[2014,2,13]]}},"container-title":["2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6747109\/6757318\/06757416.pdf?arnumber=6757416","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:23:17Z","timestamp":1490304197000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6757416\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2014.6757416","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}