{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:00:11Z","timestamp":1759147211701},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/isscc.2014.6757432","type":"proceedings-article","created":{"date-parts":[[2014,3,7]],"date-time":"2014-03-07T22:14:09Z","timestamp":1394230449000},"source":"Crossref","is-referenced-by-count":14,"title":["16.1 A 340mV-to-0.9V 20.2Tb\/s source-synchronous hybrid packet\/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS"],"prefix":"10.1109","author":[{"given":"Gregory","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark A.","family":"Anders","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Himanshu","family":"Kaul","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudhir K.","family":"Satpathy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanu K.","family":"Mathew","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven K.","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Agarwal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ram K.","family":"Krishnamurthy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shekhar","family":"Borkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6478969"},{"key":"2","first-page":"56","article-title":"A 65nm 39GOPS\/W 24-core processor with 11Tb\/s\/W packetcontrolled circuit-switched double-layer network-on-chip and heterogeneous execution array","author":"ou","year":"2013","journal-title":"ISSCC Dig Tech Papers"},{"key":"1","first-page":"88","article-title":"TILE64-processor: A 64-core SoC with mesh interconnect","author":"bell","year":"2008","journal-title":"ISSCC Dig Tech Papers"},{"key":"5","first-page":"110","article-title":"A 4.1Tb\/s bisection-bandwidth 560Gb\/s\/W streaming circuit-switched 8\ufffd8 mesh network-on-chip in 45nm CMOS","author":"anders","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"4","first-page":"178","article-title":"A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS","author":"hsu","year":"2012","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2014 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2014,2,9]]},"end":{"date-parts":[[2014,2,13]]}},"container-title":["2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6747109\/6757318\/06757432.pdf?arnumber=6757432","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:23:18Z","timestamp":1490304198000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6757432\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2014.6757432","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}