{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,30]],"date-time":"2025-08-30T17:08:13Z","timestamp":1756573693929},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/isscc.2015.7062926","type":"proceedings-article","created":{"date-parts":[[2015,3,20]],"date-time":"2015-03-20T13:20:29Z","timestamp":1426857629000},"page":"1-3","source":"Crossref","is-referenced-by-count":9,"title":["3.6 A 10Gb\/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS"],"prefix":"10.1109","author":[{"given":"Ayman","family":"Shafik","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ehsan Zhian","family":"Tabasy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shengchang","family":"Cai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keytaek","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sebastian","family":"Hoyos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuel","family":"Palermo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2011.6100209"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487625"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/49.87640"},{"key":"ref5","first-page":"274","article-title":"A 6b 10GS\/s TI-SAR ADC with embedded 2-tap FFE\/1-tap DFE in 65nm CMOS","author":"zhian tabasy","year":"2013","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185356"},{"key":"ref1","first-page":"436","article-title":"A 12.5Gb\/s SerDes in 65nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery","author":"harwood","year":"2007","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2015 IEEE International Solid- State Circuits Conference - (ISSCC)","start":{"date-parts":[[2015,2,22]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2015,2,26]]}},"container-title":["2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7054075\/7062838\/07062926.pdf?arnumber=7062926","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T19:15:48Z","timestamp":1490296548000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7062926\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2015.7062926","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}