{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T06:52:32Z","timestamp":1725778352685},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/isscc.2015.7062970","type":"proceedings-article","created":{"date-parts":[[2015,3,20]],"date-time":"2015-03-20T17:20:29Z","timestamp":1426872029000},"page":"1-3","source":"Crossref","is-referenced-by-count":20,"title":["8.4 A 0.33V\/-40°C process\/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing"],"prefix":"10.1109","author":[{"given":"Sylvain","family":"Clerc","sequence":"first","affiliation":[]},{"given":"Mehdi","family":"Saligane","sequence":"additional","affiliation":[]},{"given":"Fady","family":"Abouzeid","sequence":"additional","affiliation":[]},{"given":"Martin","family":"Cochet","sequence":"additional","affiliation":[]},{"given":"Jean-Marc","family":"Daveau","sequence":"additional","affiliation":[]},{"given":"Cyril","family":"Bottoni","sequence":"additional","affiliation":[]},{"given":"David","family":"Bol","sequence":"additional","affiliation":[]},{"given":"Julien","family":"De-Vos","sequence":"additional","affiliation":[]},{"given":"Dominique","family":"Zamora","sequence":"additional","affiliation":[]},{"given":"Benjamin","family":"Coeffic","sequence":"additional","affiliation":[]},{"given":"Dimitri","family":"Soussan","sequence":"additional","affiliation":[]},{"given":"Damien","family":"Croain","sequence":"additional","affiliation":[]},{"given":"Mehdi","family":"Naceur","sequence":"additional","affiliation":[]},{"given":"Pierre","family":"Schamberger","sequence":"additional","affiliation":[]},{"given":"Philippe","family":"Roche","sequence":"additional","affiliation":[]},{"given":"Dennis","family":"Sylvester","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"112","article-title":"Tunable Replica Circuits and Adaptative Voltage-Frequency Techniques for Dynamic Voltage, Temperature and Aging Variation Tolerance","author":"tschanz","year":"2009","journal-title":"IEEE Symp VLSI Circuits"},{"key":"ref3","first-page":"208","article-title":"A 0.16mm2 Completely On-Chip Switched-Capacitor DC-DC Converter Using Digital Capacitance Replacement in 45nm CMOS","author":"ramadass","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref2","first-page":"33","article-title":"A 0.5V 10MHz-to-100MHz 0.47?W power scalable AD-PLL in 40nm CMOS","author":"hiraku","year":"2012","journal-title":"IEEE Asian Solid-State Circuits Conf"},{"key":"ref1","first-page":"452","article-title":"A 460MHz 397mV, 2.6GHz at 1.3V, 32b VLlW DSP, Embedding Fmax Tracking","author":"wilson","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"}],"event":{"name":"2015 IEEE International Solid- State Circuits Conference - (ISSCC)","start":{"date-parts":[[2015,2,22]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2015,2,26]]}},"container-title":["2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7054075\/7062838\/07062970.pdf?arnumber=7062970","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T23:15:44Z","timestamp":1490310944000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7062970\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isscc.2015.7062970","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}