{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T05:53:11Z","timestamp":1776923591489,"version":"3.51.2"},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,1]]},"DOI":"10.1109\/isscc.2016.7417918","type":"proceedings-article","created":{"date-parts":[[2016,3,25]],"date-time":"2016-03-25T20:32:21Z","timestamp":1458937941000},"page":"84-86","source":"Crossref","is-referenced-by-count":58,"title":["4.7 A 65nm ReRAM-enabled nonvolatile processor with 6\u00d7 reduction in restore time and 4\u00d7 higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic"],"prefix":"10.1109","author":[{"given":"Yongpan","family":"Liu","sequence":"first","affiliation":[]},{"given":"Zhibo","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Albert","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Fang","family":"Su","sequence":"additional","affiliation":[]},{"given":"Chieh-Pu","family":"Lo","sequence":"additional","affiliation":[]},{"given":"Zhe","family":"Yuan","sequence":"additional","affiliation":[]},{"given":"Chien-Chen","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Qi","family":"Wei","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Ya-Chin","family":"King","sequence":"additional","affiliation":[]},{"given":"Chrong-Jung","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Pedram","family":"Khalili","sequence":"additional","affiliation":[]},{"given":"Kang-Lung","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"76c","article-title":"RRAM-based 7T1R Nonvolatile SRAM with 2x Reduction in Store Energy and 94x Reduction in Restore Energy for Frequent-Off Instant-On Applications","author":"lee","year":"2015","journal-title":"IEEE Symp VLSI Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757392"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177079"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757457"},{"key":"ref2","first-page":"432","article-title":"An 8MHz 75&#x00B5;A\/MHz Zero-Leakage Non-Volatile Logic-Based Cortex-M0 MCU SoC Exhibiting 100% Digital State Retention at VDD=0V with <400ns Wakeup and Sleep Transitions","author":"bartling","year":"2013","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341281"}],"event":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2016,1,31]]},"end":{"date-parts":[[2016,2,4]]}},"container-title":["2016 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7405163\/7417881\/7417918.pdf?arnumber=7417918","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T23:58:57Z","timestamp":1475193537000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7417918\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,1]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2016.7417918","relation":{},"subject":[],"published":{"date-parts":[[2016,1]]}}}