{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,30]],"date-time":"2026-04-30T16:26:28Z","timestamp":1777566388845,"version":"3.51.4"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,1]]},"DOI":"10.1109\/isscc.2016.7417995","type":"proceedings-article","created":{"date-parts":[[2016,3,25]],"date-time":"2016-03-25T20:32:21Z","timestamp":1458937941000},"page":"238-239","source":"Crossref","is-referenced-by-count":23,"title":["13.1 A 940MHz-bandwidth 28.8\u00b5s-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications"],"prefix":"10.1109","author":[{"given":"Hwanseok","family":"Yeo","sequence":"first","affiliation":[]},{"given":"Sigang","family":"Ryu","sequence":"additional","affiliation":[]},{"given":"Yoontaek","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Seuk","family":"Son","sequence":"additional","affiliation":[]},{"given":"Jaeha","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/JSSC.2014.2301764","article-title":"A 56.4-to-63.4GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65nm CMOS","author":"wu","year":"2014","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref3","first-page":"292","article-title":"A 1.5GHz-Modulation-Range 10ms-Modulation-Period 180kHzrms-Frequency-Error 26MHz-Reference Mixed-Mode FMCW Synthesizer","author":"sakurai","year":"2011","journal-title":"ISSCC Technical Papers"},{"key":"ref6","first-page":"136","author":"jang","year":"2015","journal-title":"IEEE Symp VLSI Circuits"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"245","DOI":"10.1109\/TEMC.2008.2012115","article-title":"A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial ATA Applications Using Two-Point Modulation","author":"kao","year":"2009","journal-title":"IEEE Trans Eiectromea Comost"},{"key":"ref8","first-page":"1","author":"ryu","year":"2013","journal-title":"Custom Integ Circuits Conf IEEE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MWSYM.2006.249848"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433951"},{"key":"ref9","first-page":"1296","article-title":"Improving CDR Performance via Estimation","author":"lee","year":"2006","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSYM.2013.6697485"}],"event":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2016,1,31]]},"end":{"date-parts":[[2016,2,4]]}},"container-title":["2016 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7405163\/7417881\/7417995.pdf?arnumber=7417995","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T09:19:39Z","timestamp":1498295979000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7417995\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,1]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/isscc.2016.7417995","relation":{},"subject":[],"published":{"date-parts":[[2016,1]]}}}