{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T01:19:22Z","timestamp":1725758362789},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,1]]},"DOI":"10.1109\/isscc.2016.7418038","type":"proceedings-article","created":{"date-parts":[[2016,3,25]],"date-time":"2016-03-25T20:32:21Z","timestamp":1458937941000},"page":"324-325","source":"Crossref","is-referenced-by-count":2,"title":["19.1 A 0.5-to-9.5GHz 1.2\u00b5s-lock-time fractional-N DPLL with \u00b11.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC"],"prefix":"10.1109","author":[{"given":"Fazil","family":"Ahmad","sequence":"first","affiliation":[]},{"given":"Greg","family":"Unruh","sequence":"additional","affiliation":[]},{"given":"Amrutha","family":"Iyer","sequence":"additional","affiliation":[]},{"given":"Pin-En","family":"Su","sequence":"additional","affiliation":[]},{"given":"Sherif","family":"Abdalla","sequence":"additional","affiliation":[]},{"given":"Bo","family":"Shen","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Chambers","sequence":"additional","affiliation":[]},{"given":"Ichiro","family":"Fujimori","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523284"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2235126"},{"key":"ref5","first-page":"96","article-title":"A Scalable Sub-1.2 mW 300 MHz-to-1.5 GHz Host-Clock PLL for System-on-Chip in 32 nm CMOS","author":"lee","year":"2011","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref2","first-page":"478","article-title":"A 1.4ps Period-Jitter TDC-Less Fractional-N Digital PLL with Digitally Controlled Ring Oscillator in 65nm CMOS","author":"grollitsch","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","first-page":"246","article-title":"A TDC-Less ADPLL with 200-to-3200 MHz Range and 3mw Power Dissipation for Mobile Soc Clocking in 22nm CMOS","author":"august","year":"2012","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","start":{"date-parts":[[2016,1,31]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2016,2,4]]}},"container-title":["2016 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7405163\/7417881\/7418038.pdf?arnumber=7418038","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,30]],"date-time":"2016-09-30T00:07:11Z","timestamp":1475194031000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7418038\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,1]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2016.7418038","relation":{},"subject":[],"published":{"date-parts":[[2016,1]]}}}