{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T22:40:51Z","timestamp":1725748851889},"reference-count":3,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/isscc.2017.7870255","type":"proceedings-article","created":{"date-parts":[[2017,3,7]],"date-time":"2017-03-07T19:34:02Z","timestamp":1488915242000},"page":"50-51","source":"Crossref","is-referenced-by-count":13,"title":["3.1 POWER9\u2122: A processor family optimized for cognitive computing with 25Gb\/s accelerator links and 16Gb\/s PCIe Gen4"],"prefix":"10.1109","author":[{"given":"Christopher","family":"Gonzalez","sequence":"first","affiliation":[]},{"given":"Eric","family":"Fluhr","sequence":"additional","affiliation":[]},{"given":"Daniel","family":"Dreps","sequence":"additional","affiliation":[]},{"given":"David","family":"Hogenmiller","sequence":"additional","affiliation":[]},{"given":"Rahul","family":"Rao","sequence":"additional","affiliation":[]},{"given":"Jose","family":"Paredes","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Floyd","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Sperling","sequence":"additional","affiliation":[]},{"given":"Ryan","family":"Kruse","sequence":"additional","affiliation":[]},{"given":"Vinod","family":"Ramadurai","sequence":"additional","affiliation":[]},{"given":"Ryan","family":"Nett","sequence":"additional","affiliation":[]},{"given":"Saiful","family":"Islam","sequence":"additional","affiliation":[]},{"given":"Juergen","family":"Pille","sequence":"additional","affiliation":[]},{"given":"Donald","family":"Plass","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref3","first-page":"96","article-title":"POWER8™: A 12-Core Server-Class Processor in 22nm SOl with 7.6Tb\/s Off-Chip Bandwidth","author":"fluhr","year":"2014","journal-title":"ISSCC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2016.7936223"},{"key":"ref1","first-page":"3.8.1","article-title":"High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 embedded DRAM and 15 Levels of Cu Metallization","author":"lin","year":"2014","journal-title":"IEDM"}],"event":{"name":"2017 IEEE International Solid- State Circuits Conference - (ISSCC)","start":{"date-parts":[[2017,2,5]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2017,2,9]]}},"container-title":["2017 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7866667\/7870233\/07870255.pdf?arnumber=7870255","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,3]],"date-time":"2017-10-03T03:51:53Z","timestamp":1507002713000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7870255\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/isscc.2017.7870255","relation":{},"subject":[],"published":{"date-parts":[[2017,2]]}}}