{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,12]],"date-time":"2026-06-12T16:41:20Z","timestamp":1781282480205,"version":"3.54.1"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/isscc.2017.7870288","type":"proceedings-article","created":{"date-parts":[[2017,3,7]],"date-time":"2017-03-07T14:34:02Z","timestamp":1488897242000},"page":"116-117","source":"Crossref","is-referenced-by-count":34,"title":["6.4 A 64Gb\/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ\/b energy efficiency in 28nm CMOS FDSOI"],"prefix":"10.1109","author":[{"given":"Giovanni","family":"Steffan","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Emanuele","family":"Depaoli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Enrico","family":"Monaco","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nicolo","family":"Sabatino","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Walter","family":"Audoglio","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Augusto Andrea","family":"Rossi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Simone","family":"Erba","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matteo","family":"Bassi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea","family":"Mazzanti","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"58","article-title":"A 36Gb\/s PAM4 transmitter using an 8b 18GS\/S DAC in 28nm CMOS","author":"nazemi","year":"2015","journal-title":"ISSCC"},{"key":"ref3","first-page":"2061","article-title":"Design of 56Gb\/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies","volume":"50","author":"lee","year":"2015","journal-title":"IEEE JSSC"},{"key":"ref6","first-page":"335","article-title":"A 0.2&#x2013;11.7GHz, high accuracy injection-locking multiphase generation with mixed analog\/digital calibration loops in 28nm FDSOI CMOS","author":"anzalone","year":"2016","journal-title":"ESSCIRC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417909"},{"key":"ref7","first-page":"763","article-title":"A 32&#x2013;48Gb\/s Serializing Transmitter Using Multiphase Serialization in 65nm CMOS Technology","volume":"50","author":"hafez","year":"2015","journal-title":"IEEE JSSC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062925"},{"key":"ref1","year":"0","journal-title":"Optical Interconnect Forum"}],"event":{"name":"2017 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2017,2,5]]},"end":{"date-parts":[[2017,2,9]]}},"container-title":["2017 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7866667\/7870233\/07870288.pdf?arnumber=7870288","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T06:37:13Z","timestamp":1489819033000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7870288\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/isscc.2017.7870288","relation":{},"subject":[],"published":{"date-parts":[[2017,2]]}}}