{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:59:55Z","timestamp":1761663595143},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/isscc.2017.7870307","type":"proceedings-article","created":{"date-parts":[[2017,3,7]],"date-time":"2017-03-07T14:34:02Z","timestamp":1488897242000},"page":"154-155","source":"Crossref","is-referenced-by-count":7,"title":["8.7 A 0.0047mm<sup>2<\/sup> highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of f&lt;inf&gt;REF&lt;\/inf&gt; to 1GHz"],"prefix":"10.1109","author":[{"given":"Hwasuk","family":"Cho","sequence":"first","affiliation":[]},{"given":"Kihwan","family":"Seong","sequence":"additional","affiliation":[]},{"given":"Kwang-Hee","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Jin-Hyeok","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Hong-June","family":"Park","sequence":"additional","affiliation":[]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"252","article-title":"A 0.048mm2 2mW Synthesizable Fractional-N PLL with a Soft lnjection-Locking Technique","author":"deng","year":"2015","journal-title":"ISSGG"},{"key":"ref3","first-page":"266","article-title":"A 0.0066mm2 780&#x00B5;W Fully Synthesizable PLL with AaCurrent-Output DAC And An Interpolative Phase-Coupled Oscillator Using Edge-Injection Techniaue","author":"deng","year":"2014","journal-title":"\/SSCC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418039"},{"key":"ref5","first-page":"268","article-title":"A 0.012mm2 3.1 mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Frequency Divider","author":"liu","year":"2014","journal-title":"ISSGG"},{"key":"ref2","first-page":"250","article-title":"A 0.032mm2 3.1 mW Synthesized Pixel Clock Generator with 30psms Integrated Jitter And 10-To-630mhz DCO Tuning Range","author":"kim","year":"2013","journal-title":"ISSCC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055347"}],"event":{"name":"2017 IEEE International Solid- State Circuits Conference - (ISSCC)","start":{"date-parts":[[2017,2,5]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2017,2,9]]}},"container-title":["2017 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7866667\/7870233\/07870307.pdf?arnumber=7870307","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T06:34:54Z","timestamp":1489818894000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7870307\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2017.7870307","relation":{},"subject":[],"published":{"date-parts":[[2017,2]]}}}