{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:54:43Z","timestamp":1780674883760,"version":"3.54.1"},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/isscc.2017.7870333","type":"proceedings-article","created":{"date-parts":[[2017,3,7]],"date-time":"2017-03-07T14:34:02Z","timestamp":1488897242000},"page":"206-207","source":"Crossref","is-referenced-by-count":63,"title":["12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V&lt;inf&gt;MIN&lt;\/inf&gt; applications"],"prefix":"10.1109","author":[{"given":"Jonathan","family":"Chang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yen-Huei","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei-Min","family":"Chan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sahil Preet","family":"Singh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hank","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hidehiro","family":"Fujiwara","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jih-Yu","family":"Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kao-Cheng","family":"Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John","family":"Hung","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Robin","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hung-Jen","family":"Liao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jhon-Jhy","family":"Liaw","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Quincy","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chih-Yung","family":"Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mu-Chi","family":"Chiang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shien-Yang","family":"Wu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active Vmin Enhanced Assist Circuitry","author":"karl","year":"2012","journal-title":"ISSCC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746307"},{"key":"ref6","first-page":"238","article-title":"A 16nm 128Mb SRAM in High-K Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMIN Applications","author":"chen","year":"2014","journal-title":"ISSCC"},{"key":"ref5","first-page":"316","article-title":"A 20nm 112Mb SRAM in High-K Metal-Gate with Assist Circuitry for Low-Leakage and Low-Vmin Applications","author":"chang","year":"2013","journal-title":"ISSCC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131655"},{"key":"ref1","first-page":"348","article-title":"A Configurable SRAM with Constant-Negative-Level Write Buffer for Low-Voltage Operation with 0.149um2 Cell in 32nm High-K Metal-Gate CMOS","author":"fujimura","year":"2010","journal-title":"ISSCC"}],"event":{"name":"2017 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2017,2,5]]},"end":{"date-parts":[[2017,2,9]]}},"container-title":["2017 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7866667\/7870233\/07870333.pdf?arnumber=7870333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T06:38:43Z","timestamp":1489819123000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7870333\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2017.7870333","relation":{},"subject":[],"published":{"date-parts":[[2017,2]]}}}