{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T16:43:08Z","timestamp":1774716188974,"version":"3.50.1"},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,2]]},"DOI":"10.1109\/isscc.2017.7870452","type":"proceedings-article","created":{"date-parts":[[2017,3,7]],"date-time":"2017-03-07T14:34:02Z","timestamp":1488897242000},"page":"444-445","source":"Crossref","is-referenced-by-count":46,"title":["26.5 Adaptive clocking in the POWER9\u2122 processor for voltage droop protection"],"prefix":"10.1109","author":[{"given":"Michael S.","family":"Floyd","sequence":"first","affiliation":[]},{"given":"Phillip J.","family":"Restle","sequence":"additional","affiliation":[]},{"given":"Michael A.","family":"Sperling","sequence":"additional","affiliation":[]},{"given":"Pawel","family":"Owczarczyk","sequence":"additional","affiliation":[]},{"given":"Eric J.","family":"Fluhr","sequence":"additional","affiliation":[]},{"given":"Joshua","family":"Friedrich","sequence":"additional","affiliation":[]},{"given":"Paul","family":"Muench","sequence":"additional","affiliation":[]},{"given":"Timothy","family":"Diemoz","sequence":"additional","affiliation":[]},{"given":"Pierce","family":"Chuang","sequence":"additional","affiliation":[]},{"given":"Christos","family":"Vezyrtzis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"400","article-title":"Razor II: In Situ Error Detection and Correction for PVR and SER Tolerance","author":"blaauw","year":"2008","journal-title":"ISSCC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref6","first-page":"398","article-title":"A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor","author":"drake","year":"2008","journal-title":"ISSCC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757358"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2237972"},{"key":"ref1","first-page":"80","article-title":"A 16nm FinFET Heterogeneous Nona-core SoC Complying with IS026262 ASIL-B: Achieving 10–7 Random Hardware Failures per Hour reliability","author":"takahashi","year":"2016","journal-title":"ISSCC"}],"event":{"name":"2017 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2017,2,5]]},"end":{"date-parts":[[2017,2,9]]}},"container-title":["2017 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7866667\/7870233\/07870452.pdf?arnumber=7870452","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T15:30:03Z","timestamp":1513179003000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7870452\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2017.7870452","relation":{},"subject":[],"published":{"date-parts":[[2017,2]]}}}