{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:26:35Z","timestamp":1772119595462,"version":"3.50.1"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,2]]},"DOI":"10.1109\/isscc.2018.8310212","type":"proceedings-article","created":{"date-parts":[[2018,3,16]],"date-time":"2018-03-16T15:53:18Z","timestamp":1521215598000},"page":"118-120","source":"Crossref","is-referenced-by-count":18,"title":["A 0.0056mm<sup>2<\/sup> all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fs&lt;inf&gt;rms&lt;\/inf&gt; Jitter and \u2212249dB FOM"],"prefix":"10.1109","author":[{"given":"Shiheng","family":"Yang","sequence":"first","affiliation":[]},{"given":"Jun","family":"Yin","sequence":"additional","affiliation":[]},{"given":"Pui-In","family":"Mak","sequence":"additional","affiliation":[]},{"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"152","article-title":"A 2. 5-to-5. 75GHz 5mW 0. 3psrms-Jitter Cascaded Ring-Based Digital Injection-Locked Clock Multiplier in 65nm CMOS","author":"coombs","year":"2017","journal-title":"ISSCC"},{"key":"ref3","first-page":"326","article-title":"A 0. 2-to-1. 45GHz Subsampling Fractional-N All-Digital MOLL with Zero-Offset Aperture PO-Based Spur Cancellation and In-Situ Timing Mismatch Detection","author":"kubdu","year":"2016","journal-title":"ISSCC"},{"key":"ref5","first-page":"150","article-title":"A 0. 42ps-Jitter-241. 7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO","author":"ngo","year":"2017","journal-title":"ISSCC"},{"key":"ref2","first-page":"328","article-title":"A 2. 4GHz 1. 5mW Digital MDLL Using Pulse-Width Comparator and Double Injection Technique in 28nm CMOS","author":"kim","year":"2016","journal-title":"ISSCC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417973"}],"event":{"name":"2018 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA","start":{"date-parts":[[2018,2,11]]},"end":{"date-parts":[[2018,2,15]]}},"container-title":["2018 IEEE International Solid - State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8304413\/8310156\/08310212.pdf?arnumber=8310212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,4,18]],"date-time":"2018-04-18T21:58:06Z","timestamp":1524088686000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8310212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2018.8310212","relation":{},"subject":[],"published":{"date-parts":[[2018,2]]}}}