{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,27]],"date-time":"2026-09-27T09:22:42Z","timestamp":1790500962975,"version":"4.1.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2018,2,1]],"date-time":"2018-02-01T00:00:00Z","timestamp":1517443200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2018,2,1]],"date-time":"2018-02-01T00:00:00Z","timestamp":1517443200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2018,2,1]],"date-time":"2018-02-01T00:00:00Z","timestamp":1517443200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,2]]},"DOI":"10.1109\/isscc.2018.8310214","type":"proceedings-article","created":{"date-parts":[[2018,3,16]],"date-time":"2018-03-16T11:53:18Z","timestamp":1521201198000},"page":"122-124","source":"Crossref","is-referenced-by-count":20,"title":["A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC"],"prefix":"10.1109","author":[{"given":"Minseob","family":"Lee","sequence":"first","affiliation":[{"name":"Pohang University of Science and Technology","place":["Pohang, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shinwoong","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Electronics","place":["Hwaseong, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hwasuk","family":"Cho","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology","place":["Pohang, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jahyun","family":"Koo","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology","place":["Pohang, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kwang-Hee","family":"Choi","sequence":"additional","affiliation":[{"name":"Samsung Electronics","place":["Hwaseong, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jin-Hyeok","family":"Choi","sequence":"additional","affiliation":[{"name":"Samsung Electronics","place":["Hwaseong, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology","place":["Pohang, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hong-June","family":"Park","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology","place":["Pohang, Korea"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology","place":["Pohang, Gyeongsangbuk-do, KR"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"252","article-title":"A 0. 048mm2 3mW Synthesizable Fractional-N PLL with a Soft Iniection-Locking Technique","author":"deng","year":"2015","journal-title":"ISSCC"},{"key":"ref3","first-page":"391","article-title":"A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC","volume":"51","author":"kim","year":"2016","journal-title":"IEEE JSSC"},{"key":"ref6","first-page":"268","article-title":"A 0. 012mm2 3. 1 mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Freauency Divider","author":"liu","year":"2014","journal-title":"ISSCC"},{"key":"ref5","first-page":"154","article-title":"A 0. 0047mm2 Highly Synthesizable TDC-and DCO-Less Fractional-N PLL with a Seamless Lock Range of fREF to 1 GHz","author":"cho","year":"2017","journal-title":"ISSCC"},{"key":"ref8","first-page":"330","article-title":"A 2. 4GHz RF Fractional-N Synthesizer with 0. 25fREF BW","author":"kong","year":"2017","journal-title":"ISSCC"},{"key":"ref7","first-page":"260","article-title":"A 1. 22ps Integrated-Jitter 0. 25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS","author":"tsai","year":"2015","journal-title":"ISSCC"},{"key":"ref2","first-page":"338","article-title":"A 0. 0021 mm21. 82mW 2. 2GHz PLL Using Time-Based Integral Control in 65nm CMOS","author":"zhu","year":"2016","journal-title":"ISSCC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176995"}],"event":{"name":"2018 IEEE International Solid-State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2018,2,11]]},"end":{"date-parts":[[2018,2,15]]}},"container-title":["2018 IEEE International Solid-State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8304413\/8310156\/08310214.pdf?arnumber=8310214","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,8,13]],"date-time":"2026-08-13T19:09:35Z","timestamp":1786648175000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8310214\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/isscc.2018.8310214","relation":{},"subject":[],"published":{"date-parts":[[2018,2]]}}}