{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,22]],"date-time":"2026-09-22T16:22:09Z","timestamp":1790094129338,"version":"4.0.1"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/isscc.2019.8662302","type":"proceedings-article","created":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T19:16:55Z","timestamp":1552936615000},"page":"142-144","source":"Crossref","is-referenced-by-count":149,"title":["7.7 LNPU: A 25.3TFLOPS\/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16"],"prefix":"10.1109","author":[{"given":"Jinsu","family":"Lee","sequence":"first","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Juhyoung","family":"Lee","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Donghyeon","family":"Han","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jinmook","family":"Lee","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gwangtae","family":"Park","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hoi-Jun","family":"Yoo","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00063"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502404"},{"key":"ref6","first-page":"35","article-title":"A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Training and Inference","author":"fleischer","year":"2018","journal-title":"IEEE Symp VLSI Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001138"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310261"}],"event":{"name":"2019 IEEE International Solid-State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2019,2,17]]},"end":{"date-parts":[[2019,2,21]]}},"container-title":["2019 IEEE International Solid-State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8656625\/8662285\/08662302.pdf?arnumber=8662302","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,25]],"date-time":"2025-08-25T20:28:59Z","timestamp":1756153739000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8662302\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc.2019.8662302","relation":{},"subject":[],"published":{"date-parts":[[2019,2]]}}}