{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:45:34Z","timestamp":1771703134758,"version":"3.50.1"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/isscc.2019.8662378","type":"proceedings-article","created":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T23:16:55Z","timestamp":1552951015000},"page":"488-490","source":"Crossref","is-referenced-by-count":7,"title":["30.8 A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fs<inf>rms<\/inf> Integrated Jitter and -256.4dB FoM"],"prefix":"10.1109","author":[{"given":"Zhao","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Guang","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"C. Patrick","family":"Yue","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227603"},{"key":"ref3","first-page":"256","article-title":"A 0.01 mm2 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with -254dB FOM","author":"sharkia","year":"2018","journal-title":"ISSCC"},{"key":"ref5","first-page":"2805","article-title":"A Near-Threshold 480MHz 78?W All-digital PLL With a Bootstrapped DCO","volume":"48","author":"ho","year":"2013","journal-title":"IEEE JSSC"},{"key":"ref2","first-page":"1630","article-title":"A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With a FoM of -250 dB","volume":"51","author":"narayanan","year":"2016","journal-title":"IEEE JSSC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338420"}],"event":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2019,2,17]]},"end":{"date-parts":[[2019,2,21]]}},"container-title":["2019 IEEE International Solid- State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8656625\/8662285\/08662378.pdf?arnumber=8662378","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:21:47Z","timestamp":1658262107000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8662378\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2019.8662378","relation":{},"subject":[],"published":{"date-parts":[[2019,2]]}}}