{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T14:35:43Z","timestamp":1777127743127,"version":"3.51.4"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/isscc.2019.8662416","type":"proceedings-article","created":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T19:16:55Z","timestamp":1552936615000},"page":"338-340","source":"Crossref","is-referenced-by-count":15,"title":["20.6 An 80MHz-BW 31.9fJ\/conv-step Filtering \u0394\u03a3 ADC with a Built-In DAC-Segmentation\/ELD-Compensation 6b 960MS\/s SAR-Quantizer in 28nm LP for 802.11ax Applications"],"prefix":"10.1109","author":[{"given":"Chi-Yun","family":"Wang","sequence":"first","affiliation":[]},{"given":"Jen-Huan","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Sheng-Yuan","family":"Su","sequence":"additional","affiliation":[]},{"given":"Jen-Che","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Jhy-Rong","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Chih-Hong","family":"Lou","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"292c","article-title":"A 13-ENOB, 5 MHz BW, 3.16 mW Multi-Bit Continuous-Time $\\Delta \\Sigma $ ADC in 28 nm CMOS with Excess-Loop-Delay Compensation Embedded in SAR Quantizer","author":"wei","year":"2015","journal-title":"IEEE Symp VLSI Circuits"},{"key":"ref3","first-page":"1535","article-title":"A Filtering $\\Delta \\Sigma $ ADC for LTE and Beyond","volume":"49","author":"andersson","year":"2014","journal-title":"IEEE JSSC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042244"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870465"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858396"}],"event":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2019,2,17]]},"end":{"date-parts":[[2019,2,21]]}},"container-title":["2019 IEEE International Solid- State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8656625\/8662285\/08662416.pdf?arnumber=8662416","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T16:22:52Z","timestamp":1658247772000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8662416\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2019.8662416","relation":{},"subject":[],"published":{"date-parts":[[2019,2]]}}}