{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T14:34:09Z","timestamp":1777127649196,"version":"3.51.4"},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/isscc.2019.8662464","type":"proceedings-article","created":{"date-parts":[[2019,3,18]],"date-time":"2019-03-18T23:16:55Z","timestamp":1552951015000},"page":"262-264","source":"Crossref","is-referenced-by-count":14,"title":["6.4 A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation"],"prefix":"10.1109","author":[{"given":"Szu-Yao","family":"Hung","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudhakar","family":"Pamarti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.916571"},{"key":"ref3","first-page":"272","article-title":"A 20-to-1000MHz ±14ps Peak-to-Peak Jitter Reconfigurable Multi-Output All-Digital Clock Generator Using Open-Loop Fractional Dividers in 65nm CMOS","author":"elkholy","year":"2014","journal-title":"ISSCC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417971"},{"key":"ref1","first-page":"258","article-title":"A 5GHz-95dBc-Reference-Spur 9.5mW Digital Fractional-N PLL Using Reference-Multiplied Time-to-Digital Converter and Reference-Spur Cancellation in 65nm CMOS","author":"kim","year":"2015","journal-title":"ISSCC"}],"event":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2019,2,17]]},"end":{"date-parts":[[2019,2,21]]}},"container-title":["2019 IEEE International Solid- State Circuits Conference - (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8656625\/8662285\/08662464.pdf?arnumber=8662464","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:18:05Z","timestamp":1658261885000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8662464\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isscc.2019.8662464","relation":{},"subject":[],"published":{"date-parts":[[2019,2]]}}}