{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T07:35:59Z","timestamp":1780472159845,"version":"3.54.1"},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,2,13]],"date-time":"2021-02-13T00:00:00Z","timestamp":1613174400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,2,13]],"date-time":"2021-02-13T00:00:00Z","timestamp":1613174400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,2,13]],"date-time":"2021-02-13T00:00:00Z","timestamp":1613174400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006034","name":"University of Southern California","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006034","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,13]]},"DOI":"10.1109\/isscc42613.2021.9365819","type":"proceedings-article","created":{"date-parts":[[2021,3,3]],"date-time":"2021-03-03T21:23:11Z","timestamp":1614806591000},"page":"410-412","source":"Crossref","is-referenced-by-count":16,"title":["29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur"],"prefix":"10.1109","author":[{"given":"Qiaochu","family":"Zhang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shiyu","family":"Su","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cheng-Ru","family":"Ho","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mike Shuo-Wei","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310350"},{"key":"ref3","first-page":"360","article-title":"A 1.7 GHz MDLL-Based Fractional-N Frequency Synthesizer with 1.4ps RMS Integrated Jitter and 3mW Power Using a 1b TDC","author":"marucci","year":"2014","journal-title":"ISSCC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062939"},{"key":"ref1","first-page":"252","article-title":"A 0.048mm2 3mW Synthesizable Fractional-N PLL with a Soft Injection-Locked Oscillator in 65nm CMOS","author":"deng","year":"2015","journal-title":"ISSCC"}],"event":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2021,2,13]]},"end":{"date-parts":[[2021,2,22]]}},"container-title":["2021 IEEE International Solid- State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9365732\/9365735\/09365819.pdf?arnumber=9365819","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:42:09Z","timestamp":1652197329000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9365819\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,13]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/isscc42613.2021.9365819","relation":{},"subject":[],"published":{"date-parts":[[2021,2,13]]}}}