{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T08:20:47Z","timestamp":1767860447945,"version":"3.49.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,2,13]],"date-time":"2021-02-13T00:00:00Z","timestamp":1613174400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,2,13]],"date-time":"2021-02-13T00:00:00Z","timestamp":1613174400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,2,13]],"date-time":"2021-02-13T00:00:00Z","timestamp":1613174400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,13]]},"DOI":"10.1109\/isscc42613.2021.9366001","type":"proceedings-article","created":{"date-parts":[[2021,3,3]],"date-time":"2021-03-03T16:23:11Z","timestamp":1614788591000},"page":"494-496","source":"Crossref","is-referenced-by-count":6,"title":["35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon\u2122 Processor"],"prefix":"10.1109","author":[{"given":"Vijay Kiran","family":"Kalyanam","sequence":"first","affiliation":[]},{"given":"Eric","family":"Mahurin","sequence":"additional","affiliation":[]},{"given":"Keith","family":"Bowman","sequence":"additional","affiliation":[]},{"given":"Suresh","family":"Venkumahanti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.52"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062932"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838333"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075933"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2017.7918320"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSICircuits18222.2020.9162808"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859902"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477329"}],"event":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2021,2,13]]},"end":{"date-parts":[[2021,2,22]]}},"container-title":["2021 IEEE International Solid- State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9365732\/9365735\/09366001.pdf?arnumber=9366001","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T11:42:07Z","timestamp":1652182927000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9366001\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,13]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/isscc42613.2021.9366001","relation":{},"subject":[],"published":{"date-parts":[[2021,2,13]]}}}