{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,21]],"date-time":"2026-04-21T16:28:23Z","timestamp":1776788903511,"version":"3.51.2"},"reference-count":0,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,2,20]],"date-time":"2022-02-20T00:00:00Z","timestamp":1645315200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,2,20]],"date-time":"2022-02-20T00:00:00Z","timestamp":1645315200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,2,20]]},"DOI":"10.1109\/isscc42614.2022.9731565","type":"proceedings-article","created":{"date-parts":[[2022,3,17]],"date-time":"2022-03-17T20:48:08Z","timestamp":1647550088000},"page":"428-429","source":"Crossref","is-referenced-by-count":75,"title":["3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU"],"prefix":"10.1109","author":[{"given":"John","family":"Wuu","sequence":"first","affiliation":[{"name":"AMD,Fort Collins,CO"}]},{"given":"Rahul","family":"Agarwal","sequence":"additional","affiliation":[{"name":"AMD,Santa Clara,CA"}]},{"given":"Michael","family":"Ciraula","sequence":"additional","affiliation":[{"name":"AMD,Fort Collins,CO"}]},{"given":"Carl","family":"Dietz","sequence":"additional","affiliation":[{"name":"AMD,Fort Collins,CO"}]},{"given":"Brett","family":"Johnson","sequence":"additional","affiliation":[{"name":"AMD,Fort Collins,CO"}]},{"given":"Dave","family":"Johnson","sequence":"additional","affiliation":[{"name":"AMD,Fort Collins,CO"}]},{"given":"Russell","family":"Schreiber","sequence":"additional","affiliation":[{"name":"AMD,Austin,TX"}]},{"given":"Raja","family":"Swaminathan","sequence":"additional","affiliation":[{"name":"AMD,Austin,TX"}]},{"given":"Will","family":"Walker","sequence":"additional","affiliation":[{"name":"AMD,Fort Collins,CO"}]},{"given":"Samuel","family":"Naffziger","sequence":"additional","affiliation":[{"name":"AMD,Fort Collins,CO"}]}],"member":"263","event":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2022,2,20]]},"end":{"date-parts":[[2022,2,26]]}},"container-title":["2022 IEEE International Solid- State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9731529\/9731102\/09731565.pdf?arnumber=9731565","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,10]],"date-time":"2022-06-10T21:17:21Z","timestamp":1654895841000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9731565\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,2,20]]},"references-count":0,"URL":"https:\/\/doi.org\/10.1109\/isscc42614.2022.9731565","relation":{},"subject":[],"published":{"date-parts":[[2022,2,20]]}}}