{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T16:45:29Z","timestamp":1783701929151,"version":"3.55.0"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,2,20]],"date-time":"2022-02-20T00:00:00Z","timestamp":1645315200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,2,20]],"date-time":"2022-02-20T00:00:00Z","timestamp":1645315200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,2,20]]},"DOI":"10.1109\/isscc42614.2022.9731673","type":"proceedings-article","created":{"date-parts":[[2022,3,17]],"date-time":"2022-03-17T20:48:08Z","timestamp":1647550088000},"page":"42-44","source":"Crossref","is-referenced-by-count":100,"title":["Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing"],"prefix":"10.1109","author":[{"given":"Wilfred","family":"Gomes","sequence":"first","affiliation":[{"name":"Intel,Portland,OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Altug","family":"Koker","sequence":"additional","affiliation":[{"name":"Intel,Folsom,CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pat","family":"Stover","sequence":"additional","affiliation":[{"name":"Intel,Chandler,AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Doug","family":"Ingerly","sequence":"additional","affiliation":[{"name":"Intel,Portland,OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Scott","family":"Siers","sequence":"additional","affiliation":[{"name":"Intel,Folsom,CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Srikrishnan","family":"Venkataraman","sequence":"additional","affiliation":[{"name":"Intel,Bengaluru,India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chris","family":"Pelto","sequence":"additional","affiliation":[{"name":"Intel,Portland,OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tejas","family":"Shah","sequence":"additional","affiliation":[{"name":"Intel,Austin,TX"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Amreesh","family":"Rao","sequence":"additional","affiliation":[{"name":"Intel,Folsom,CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Frank","family":"O'Mahony","sequence":"additional","affiliation":[{"name":"Intel,Portland,OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eric","family":"Karl","sequence":"additional","affiliation":[{"name":"Intel,Portland,OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lance","family":"Cheney","sequence":"additional","affiliation":[{"name":"Intel,Folsom,CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Iqbal","family":"Rajwani","sequence":"additional","affiliation":[{"name":"Intel,Folsom,CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hemant","family":"Jain","sequence":"additional","affiliation":[{"name":"Intel,Bengaluru,India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ryan","family":"Cortez","sequence":"additional","affiliation":[{"name":"Intel,Folsom,CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Arun","family":"Chandrasekhar","sequence":"additional","affiliation":[{"name":"Intel,Bengaluru,India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Basavaraj","family":"Kanthi","sequence":"additional","affiliation":[{"name":"Intel,Bengaluru,India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Raja","family":"Koduri","sequence":"additional","affiliation":[{"name":"Intel,Santa Clara,CA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"29.1.1","article-title":"A 10nm High Performance and Low-Power CMOS Technology","author":"auth","year":"2017","journal-title":"IEDM"},{"key":"ref3","first-page":"432","article-title":"Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs","author":"burton","year":"0","journal-title":"IEEE Applied Power Electronics Conf"},{"key":"ref6","first-page":"144","article-title":"Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12x12mm2, 1 mm Package-on-Package","author":"gomes","year":"2020","journal-title":"ISSCC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32696.2021.00208"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2019.2942708"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993637"}],"event":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2022,2,20]]},"end":{"date-parts":[[2022,2,26]]}},"container-title":["2022 IEEE International Solid- State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9731529\/9731102\/09731673.pdf?arnumber=9731673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T20:43:33Z","timestamp":1658177013000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9731673\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,2,20]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc42614.2022.9731673","relation":{},"subject":[],"published":{"date-parts":[[2022,2,20]]}}}