{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T23:45:58Z","timestamp":1773791158209,"version":"3.50.1"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,2,16]],"date-time":"2025-02-16T00:00:00Z","timestamp":1739664000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,2,16]],"date-time":"2025-02-16T00:00:00Z","timestamp":1739664000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,2,16]]},"DOI":"10.1109\/isscc49661.2025.10904530","type":"proceedings-article","created":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T13:33:12Z","timestamp":1741267992000},"page":"1-3","source":"Crossref","is-referenced-by-count":2,"title":["A 50Gb\/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON"],"prefix":"10.1109","author":[{"given":"Boyang","family":"Zhang","sequence":"first","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Tianchen","family":"Ye","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Shuaizhe","family":"Ma","sequence":"additional","affiliation":[{"name":"Xi&#x0027;an JiaoTono University,Xi&#x0027;an,China"}]},{"given":"Tianyuan","family":"Zhong","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Xin","family":"Liu","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Feiyang","family":"Zhang","sequence":"additional","affiliation":[{"name":"Xi&#x0027;an JiaoTono University,Xi&#x0027;an,China"}]},{"given":"Bingyi","family":"Ye","sequence":"additional","affiliation":[{"name":"East China Normal University,Shanghai,China"}]},{"given":"Dan","family":"Li","sequence":"additional","affiliation":[{"name":"Xi&#x0027;an JiaoTono University,Xi&#x0027;an,China"}]},{"given":"Weixin","family":"Gai","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1364\/JOCN.391904"},{"key":"ref2","first-page":"266","article-title":"A 56 Gb\/s burst-mode NRZ optical receiver with 6.8 ns power-on and CDR-lock time for adaptive optical links in 14 nm FinFET CMOS","volume-title":"ISSCC","author":"Ozkaya","year":"2018"},{"key":"ref3","volume-title":"G.9804.3: 50-Gigabit-capable passive optical networks (50G-PON): Physical media dependent (PMD) layer specification"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijleo.2012.04.008"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1364\/JOCN.468920"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2478837"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3211347"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865673"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3313524"},{"key":"ref10","first-page":"1","article-title":"IEEE Standard for Ethernet Amendment 9: Physical Layer Specifications and Management Parameters for 25 Gb\/s and 50 Gb\/s Passive Optical Networks","volume-title":"IEEE Std 802.3ca-2020","year":"2020"},{"key":"ref11","first-page":"1","article-title":"Real-Time FPGA Demonstration of PAM-4 Burst-Mode All-Digital Clock and Data Recovery for Single wavelength 50G PON Application","volume-title":"Optical Fiber Communications Conference and Exposition","author":"Zhang","year":"2018"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/OECC56963.2023.10209815"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3242366"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2017.2784848"}],"event":{"name":"2025 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2025,2,16]]},"end":{"date-parts":[[2025,2,20]]}},"container-title":["2025 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10904417\/10904496\/10904530.pdf?arnumber=10904530","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:15:47Z","timestamp":1773778547000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10904530\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2,16]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/isscc49661.2025.10904530","relation":{},"subject":[],"published":{"date-parts":[[2025,2,16]]}}}