{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T17:31:04Z","timestamp":1772645464974,"version":"3.50.1"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,2,16]],"date-time":"2025-02-16T00:00:00Z","timestamp":1739664000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,2,16]],"date-time":"2025-02-16T00:00:00Z","timestamp":1739664000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,2,16]]},"DOI":"10.1109\/isscc49661.2025.10904578","type":"proceedings-article","created":{"date-parts":[[2025,3,6]],"date-time":"2025-03-06T18:33:12Z","timestamp":1741285992000},"page":"288-290","source":"Crossref","is-referenced-by-count":3,"title":["16.4: SambaNova SN40L: A 5nm 2.5D Dataflow Accelerator with Three Memory Tiers for Trillion Parameter AI"],"prefix":"10.1109","author":[{"given":"Raghu","family":"Prabhakar","sequence":"first","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Junwei","family":"Zhou","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Darshan","family":"Gandhi","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Youngmoon","family":"Choi","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Mahmood","family":"Khayatzadeh","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Kyunglok","family":"Kim","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Uma","family":"Durairajan","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Jeongha","family":"Park","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Satyajit","family":"Sarkar","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]},{"given":"Jinuk Luke","family":"Shin","sequence":"additional","affiliation":[{"name":"SambaNova Systems,Palo Alto,CA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HCS61935.2024.10664717"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO61859.2024.00100"},{"key":"ref3","volume-title":"Learning to Reason with LLM","year":"2024"},{"key":"ref4","volume-title":"Scaling LLM Test-Time Compute Optimally can be More Effective than Scaling Model Parameters","author":"Snell","year":"2024"},{"key":"ref5","volume-title":"Prompt Caching","year":"2024"},{"key":"ref6","volume-title":"NVIDIA TensorRT-LLM","year":"2024"},{"key":"ref7","volume-title":"NVIDIA DGX H100 Datasheet","year":"2024"}],"event":{"name":"2025 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2025,2,16]]},"end":{"date-parts":[[2025,2,20]]}},"container-title":["2025 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10904417\/10904496\/10904578.pdf?arnumber=10904578","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,24]],"date-time":"2025-04-24T17:02:40Z","timestamp":1745514160000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10904578\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2,16]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/isscc49661.2025.10904578","relation":{},"subject":[],"published":{"date-parts":[[2025,2,16]]}}}