{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T21:06:39Z","timestamp":1772658399387,"version":"3.50.1"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2023YFB4403900"],"award-info":[{"award-number":["2023YFB4403900"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62525404,62034002,62374026"],"award-info":[{"award-number":["62525404,62034002,62374026"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,15]]},"DOI":"10.1109\/isscc49663.2026.11408980","type":"proceedings-article","created":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:50:24Z","timestamp":1772571024000},"page":"466-468","source":"Crossref","is-referenced-by-count":0,"title":["27.1 A 20GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2fs Jitter and \u221276.5dBc Worst-Case Fractional Spur"],"prefix":"10.1109","author":[{"given":"Zonglin","family":"Ye","sequence":"first","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuxuan","family":"Sun","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Longxiang","family":"Hou","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuhan","family":"Ding","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yixuan","family":"Wen","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hongyang","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinlin","family":"Geng","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qian","family":"Xie","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shiheng","family":"Yang","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zheng","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Electronic Science and Technology of China,Chengdu,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454462"},{"key":"ref2","first-page":"328","article-title":"A Fractional-N PLL with 34fsrms Jitter and \u2212255.5 dB FoM Based on a Multipath Feedback Technique","volume-title":"ISSCC","author":"Hung","year":"2025"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2022.3209614"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49661.2025.10904516"},{"key":"ref5","first-page":"336","article-title":"A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9 fsrms Jitter, 249.7 dB FoM, and $1.98 \\mu \\mathrm{s}$ Locking Time Using a Polarity-Reversible SSPD","volume-title":"ISSCC","author":"Li","year":"2025"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2023.3311681"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/cicc63670.2025.10982962"},{"key":"ref8","first-page":"196","article-title":"A $76 \\text{fs}_{\\text{rms}_{\\text{sm}}}$-Jitter and \u221265dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique","volume-title":"ISSCC","author":"Shin","year":"2024"},{"key":"ref9","first-page":"82","article-title":"A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology","volume-title":"ISSCC","author":"Castoro","year":"2023"},{"key":"ref10","first-page":"188","article-title":"An 8.75 GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3 fsrms Integrated Jitter and \u2212252.4 dB FoM","volume-title":"ISSCC","author":"Rossoni","year":"2024"},{"key":"ref11","first-page":"1","article-title":"A 37.5fs-rms Jitter and \u2212254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving $8 \\times$ DTC Range Reduction and Zero DTC Delay Offset","author":"Liu","year":"2025","journal-title":"IEEE CICC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2019.2925181"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2025.3557258"}],"event":{"name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,2,15]]},"end":{"date-parts":[[2026,2,19]]}},"container-title":["2026 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408863\/11408946\/11408980.pdf?arnumber=11408980","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T20:47:29Z","timestamp":1772657249000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11408980\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,15]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/isscc49663.2026.11408980","relation":{},"subject":[],"published":{"date-parts":[[2026,2,15]]}}}