{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T14:11:08Z","timestamp":1772633468280,"version":"3.50.1"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,15]]},"DOI":"10.1109\/isscc49663.2026.11409095","type":"proceedings-article","created":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:50:24Z","timestamp":1772571024000},"page":"140-142","source":"Crossref","is-referenced-by-count":0,"title":["8.4 A 112Gb\/S\/Wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS"],"prefix":"10.1109","author":[{"given":"Zhiwen","family":"Huang","sequence":"first","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Zhifei","family":"Wang","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Bingyi","family":"Ye","sequence":"additional","affiliation":[{"name":"East China Normal University,Shanghai,China"}]},{"given":"Tianchen","family":"Ye","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Dunshan","family":"Yu","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Wei","family":"Wang","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]},{"given":"Weixin","family":"Gai","sequence":"additional","affiliation":[{"name":"Peking University,Beijing,China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"crossref","first-page":"588","DOI":"10.1007\/s11427-024-2673-9","article-title":"A 641Gb\/s\/wire $10.5 ~\\text{Tb} \/ \\mathrm{s} \/ \\text{mm} \/$ Layer Single-Ended Simultaneous BiDirectional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS","author":"Wang","year":"2025","journal-title":"ISSCC"},{"key":"ref2","first-page":"586","article-title":"A $32 ~\\text{Gb} \/ \\mathrm{s} 10.5 ~\\text{Tb} \/ \\mathrm{s} \/ \\text{mm} 0.6 \\text{pJ} \/ \\mathrm{b}$ UCle-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating","author":"Lin","year":"2025","journal-title":"ISSCC"},{"key":"ref3","first-page":"114","article-title":"A $4 ~\\text{nm} 32 ~\\text{Gb} \/ \\mathrm{s} 8 ~\\text{Tb} \/ \\mathrm{s} \/ \\text{mm}$ Die-to-Die Chiplet Using NRZ Single-Ended Transceiver with Equalization Schemes and Training Techniques","author":"Seong","year":"2023","journal-title":"ISSCC"},{"key":"ref4","first-page":"C1","article-title":"A $246 \\text{fJ} \/ \\mathrm{b} 13.3 ~\\text{Tb} \/ \\mathrm{s} \/ \\text{mm}$ Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect","author":"Lee","year":"2024","journal-title":"IEEE Symp. VLSI Technology"},{"key":"ref5","first-page":"13","article-title":"Standing Wave Based Clock Distribution Technique with Application to a $10 \\times 11$ Gbps Transceiver in 28 nm CMOS","author":"Li","year":"2015","journal-title":"IEEE A-SSCC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/vlsic.2008.4585955"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2020.3038818"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9063162"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2022.3232024"},{"key":"ref10","first-page":"19","article-title":"A $32 ~\\text{Gb} \/ \\mathrm{s} 0.36 \\text{pJ} \/$ bit 3 nm Chiplet IO using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring","author":"Gu","year":"2024","journal-title":"IEEE Symp. VLSI Technology"}],"event":{"name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,2,15]]},"end":{"date-parts":[[2026,2,19]]}},"container-title":["2026 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408863\/11408946\/11409095.pdf?arnumber=11409095","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T07:28:03Z","timestamp":1772609283000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11409095\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,15]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/isscc49663.2026.11409095","relation":{},"subject":[],"published":{"date-parts":[[2026,2,15]]}}}