{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,31]],"date-time":"2026-10-31T20:26:18Z","timestamp":1793478378416,"version":"4.5.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,15]]},"DOI":"10.1109\/isscc49663.2026.11409147","type":"proceedings-article","created":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:50:24Z","timestamp":1772571024000},"page":"1-3","source":"Crossref","is-referenced-by-count":2,"title":["A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving \u221262dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mV\n                    <sub>rms<\/sub>\n                    DTC Supply Noise"],"prefix":"10.1109","author":[{"given":"Damiano","family":"Fagotti","sequence":"first","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Riccardo","family":"Moleri","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michele","family":"Rossoni","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniele Lodi","family":"Rizzini","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pietro","family":"Salvi","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Stefano","family":"Gallucci","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giovanni Rocco","family":"Trotta","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea Leonardo","family":"Lacaita","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Simone Mattia","family":"Dartizio","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Salvatore","family":"Levantino","sequence":"additional","affiliation":[{"name":"Politecnico di Milano,Milan,Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/mssc.2021.3111430"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ojsscs.2024.3476035"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2024.3469556"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2024.3501196"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49661.2025.10904741"},{"key":"ref6","first-page":"336","article-title":"A 27 GHz Fractional-N Sub-Sampling PLL Achieving 57.9frms Jitter, -249.7 dB FoM, and 1.98s Locking Time Using Polarity-Reversible SSPD","author":"Li","year":"2025","journal-title":"ISSCC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2022.3209338"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.4577"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2020.3047431"},{"key":"ref10","first-page":"1","article-title":"A 55.8 -to-64.2GHz, 58.3fs rms-Jitter, -250.2dB-FoM J Fractional-N Cascaded PLL in 28nm CMOS","volume-title":"IEEE Symp. VLSI Circuits","author":"Jung","year":"2025"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2021.3123386"},{"key":"ref12","first-page":"1","article-title":"A Fractional-N Digital-PLL Based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3 mV pp Supply Ripple","volume-title":"IEEE Symp. VLSI Circuits","author":"Rossoni","year":"2025"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2020.3019344"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/esscirc.2014.6942026"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2011.2162917"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2021.3111134"}],"event":{"name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,2,15]]},"end":{"date-parts":[[2026,2,19]]}},"container-title":["2026 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408863\/11408946\/11409147.pdf?arnumber=11409147","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T07:10:38Z","timestamp":1772608238000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11409147\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,15]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isscc49663.2026.11409147","relation":{},"subject":[],"published":{"date-parts":[[2026,2,15]]}}}