{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T14:06:05Z","timestamp":1772633165783,"version":"3.50.1"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,15]]},"DOI":"10.1109\/isscc49663.2026.11409228","type":"proceedings-article","created":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:50:24Z","timestamp":1772571024000},"page":"636-638","source":"Crossref","is-referenced-by-count":0,"title":["37.7 A 12.8Gb\/s Parallel Receiver with a One-Way Self-Training Scheme for Equalizing ISI and Reflections in Multi-Drop Memory Interfaces"],"prefix":"10.1109","author":[{"given":"Ji-Won","family":"Moon","sequence":"first","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taehyeon","family":"Kim","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minwook","family":"Kim","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyeonwoo","family":"Seong","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jewon","family":"Lee","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeongbin","family":"Park","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dongjun","family":"Park","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaehoon","family":"Lee","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung-June","family":"Park","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Hwaseong,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chiweon","family":"Yoon","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Hwaseong,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae-Yoon","family":"Sim","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seon-Kyoo","family":"Lee","sequence":"additional","affiliation":[{"name":"Pohang University of Science and Technology,Pohang,Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"JESD79-4B:JEDEC Standard DDR4 SDRAM","year":"2017"},{"key":"ref2","first-page":"180","article-title":"A $7.5 \\text{mW} 7.5 \\text{Gb} \/ \\mathrm{s}$ mixed NRZ\/multi-tone serial-data transceiver for multi-drop memory interfaces in 40 nm CMOS","volume-title":"ISSCC","author":"Gharibdoust","year":"2015"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2017.2675923"},{"key":"ref4","first-page":"272","article-title":"A $7.8 \\text{Gb} \/ \\mathrm{s} \/$ pin $1.96 \\text{pJ} \/ \\mathrm{b}$ compact single-ended TRX and CDR with phasedifference modulation for highly reflective memory interfaces","volume-title":"ISSCC","author":"Lee","year":"2018"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir65189.2025.11075070"}],"event":{"name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,2,15]]},"end":{"date-parts":[[2026,2,19]]}},"container-title":["2026 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408863\/11408946\/11409228.pdf?arnumber=11409228","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T07:17:34Z","timestamp":1772608654000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11409228\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,15]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc49663.2026.11409228","relation":{},"subject":[],"published":{"date-parts":[[2026,2,15]]}}}