{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T13:57:47Z","timestamp":1772632667644,"version":"3.50.1"},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,15]]},"DOI":"10.1109\/isscc49663.2026.11409321","type":"proceedings-article","created":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:50:24Z","timestamp":1772571024000},"page":"628-630","source":"Crossref","is-referenced-by-count":0,"title":["37.3 A 2nm All-Digital 14.4Gb\/s\/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE"],"prefix":"10.1109","author":[{"given":"Yoonjae","family":"Choi","sequence":"first","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Daero","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Myunggon","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Sangmin","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Hansol","family":"Kang","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Gwangwon","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Yoonhyung","family":"Kim","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Sungsik","family":"Kang","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Hyun","family":"Cho","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Boyoung","family":"Kang","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Kyoungwon","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Jaegeun","family":"Song","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Jinho","family":"Choi","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Shinyoung","family":"Yi","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Billy","family":"Koo","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Kwanyeob","family":"Chae","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]},{"given":"Hyo-Gyuem","family":"Rhew","sequence":"additional","affiliation":[{"name":"Samsung Electronics,Yongin,Korea"}]}],"member":"263","reference":[{"key":"ref1","first-page":"510","article-title":"A 16 Gb 12.7 Gb\/s\/pin LPDDR5-Ultra-Pro DRAM with 4-Phase SelfCalibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process","author":"Baek","year":"2025","journal-title":"ISSCC"},{"key":"ref2","first-page":"246","article-title":"A 1a-nm 1.05 V 10.5 Gb\/s\/pin 16 Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction","author":"Seo","year":"2024","journal-title":"ISSCC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/vlsic.2019.8777959"},{"key":"ref4","article-title":"LPDDR6 Standard","volume-title":"JESD209\u20136, JEDEC","year":"2025"},{"key":"ref5","first-page":"406","article-title":"A 4 n m 1.15 TB\/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection","author":"Chae","year":"2023","journal-title":"ISSCC"}],"event":{"name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,2,15]]},"end":{"date-parts":[[2026,2,19]]}},"container-title":["2026 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408863\/11408946\/11409321.pdf?arnumber=11409321","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T07:08:47Z","timestamp":1772608127000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11409321\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,15]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc49663.2026.11409321","relation":{},"subject":[],"published":{"date-parts":[[2026,2,15]]}}}