{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T13:50:19Z","timestamp":1772632219499,"version":"3.50.1"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,15]]},"DOI":"10.1109\/isscc49663.2026.11409328","type":"proceedings-article","created":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:50:24Z","timestamp":1772571024000},"page":"208-210","source":"Crossref","is-referenced-by-count":0,"title":["12.1 A 74fs-Jitter, -59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC"],"prefix":"10.1109","author":[{"given":"Rishabh","family":"Gurbaxani","sequence":"first","affiliation":[{"name":"TU Delft,Delft,The Netherlands"}]},{"given":"Cicero S.","family":"Vaucher","sequence":"additional","affiliation":[{"name":"TU Delft,Delft,The Netherlands"}]},{"given":"Masoud","family":"Babaie","sequence":"additional","affiliation":[{"name":"TU Delft,Delft,The Netherlands"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2024.3501196"},{"key":"ref2","first-page":"386","article-title":"A 68.6fs ${}_{\\text{rms }}$-Total-Integrated-Jitter and $1.56 \\mu \\mathrm{s}$-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching","volume-title":"ISSCC","author":"Dartizio","year":"2022"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2020.3019344"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2009.2032723"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2019.2936967"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2019.2899726"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2011.2162917"},{"key":"ref8","first-page":"246","article-title":"A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of \u2212246 dB for IoT applications in 65 nm CMOS","volume-title":"ISSCC","author":"Liu","year":"2018"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365850"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2014.2385753"},{"key":"ref11","first-page":"442","article-title":"A $365 f s_{\\text{rms}}$-Jitter and \u221263dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second\/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping $\\Delta \\Sigma \\mathrm{M}$","volume-title":"ISSCC","author":"Park","year":"2021"},{"key":"ref12","first-page":"82","article-title":"A 9.25 GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology","volume-title":"ISSCC","author":"Castoro","year":"2023"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2022.3209338"},{"key":"ref14","first-page":"78","article-title":"A 76.7fs-Integrated-Jitter and \u221271.9 dBc In-Band FractionalSpur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering","volume-title":"ISSCC","author":"Dartizio","year":"2023"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454284"},{"key":"ref16","first-page":"188","article-title":"An 8.75 GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and \u2212252.4 dB FoM","volume-title":"ISSCC","author":"Rossoni","year":"2024"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2015.2414421"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2019.2939663"},{"key":"ref19","first-page":"1728","article-title":"A $2.4-\\text{GHz}$ fractional-N PLL with a PFD\/CP linearization and an improved CP circuit","volume-title":"IEEE ISCAS","author":"Ti","year":"2008"},{"key":"ref20","first-page":"554","article-title":"A 65fs ${}_{\\text{rms}_{\\mathrm{s}}}$-Jitter and $-272 \\text{dB}-\\text{FoM}_{\\mathrm{j}_{\\text{jitter}, \\mathrm{N}}} 10.1 \\text{GHz}$ Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration","volume-title":"ISSCC","author":"Chae","year":"2025"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2014.2385753"},{"key":"ref22","first-page":"380382","article-title":"A $2.6-\\text{to}-4.1 \\text{GHz}$ Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving - 249.4 dB FoM and \u221259dBc Fractional Spurs","volume-title":"ISSCC","author":"Gao","year":"2022"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2021.3123386"}],"event":{"name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,2,15]]},"end":{"date-parts":[[2026,2,19]]}},"container-title":["2026 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408863\/11408946\/11409328.pdf?arnumber=11409328","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T06:56:10Z","timestamp":1772607370000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11409328\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,15]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/isscc49663.2026.11409328","relation":{},"subject":[],"published":{"date-parts":[[2026,2,15]]}}}