{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T20:52:22Z","timestamp":1774471942841,"version":"3.50.1"},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,15]],"date-time":"2026-02-15T00:00:00Z","timestamp":1771113600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,15]]},"DOI":"10.1109\/isscc49663.2026.11409345","type":"proceedings-article","created":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:50:24Z","timestamp":1772571024000},"page":"200-202","source":"Crossref","is-referenced-by-count":0,"title":["11.6 an 8B 20Gs\/S Time-Interleaved ADC with 2.6mW 1GS\/s Hybrid Voltage\/Time-Domain Sub-ADC in 12Nm FinFET"],"prefix":"10.1109","author":[{"given":"Daisuke","family":"Miyazaki","sequence":"first","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Yuki","family":"Yagishita","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Mika","family":"Takasaki","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Shun","family":"Nagata","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Takeru","family":"Nogamida","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Yudai","family":"Abe","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Kazutoshi","family":"Tomita","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Kazunori","family":"Hasebe","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Toshiyuki","family":"Kikkawa","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Satoshi","family":"Yoshizawa","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Atsuya","family":"Suzuki","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Soichi","family":"Kato","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Takahiro","family":"Naito","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Keigo","family":"Bunsen","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Tomohiro","family":"Matsumoto","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]},{"given":"Yasushi","family":"Katayama","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions,Atsugi,Japan"}]}],"member":"263","reference":[{"key":"ref1","first-page":"392","article-title":"A 76 mW 40GS\/s 7b Time-interleaved Hybrid Voltage\/TimeDomain ADC with Common-Mode Input Tracking","volume-title":"ISSCC","author":"Whitcombe","year":"2024"},{"key":"ref2","first-page":"252","article-title":"A 4x Interleaved 10GS\/s 8b Time-Domain ADC with $16\\times$ InterpolationBased Inter-Stage Gain Achieving >37.5 dB SNDR at 18 GHz Input","volume-title":"ISSCC","author":"Zhang","year":"2020"},{"key":"ref3","article-title":"A PVT-Robust $16 \\text{GS}\/\\mathrm{s} 4 \\times \\text{TI}$ Time-Domain ADC with Vernier-based Multipath Flash TDC achieving 25.7fJ\/c-s FoM in 28 nm CMOS","volume-title":"IEEE Symp. on VLSI Circuits, C84","author":"Li","year":"2025"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir65189.2025.11075030"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/vlsicircuits52068.2021.9492436"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454361"}],"event":{"name":"2026 IEEE International Solid-State Circuits Conference (ISSCC)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,2,15]]},"end":{"date-parts":[[2026,2,19]]}},"container-title":["2026 IEEE International Solid-State Circuits Conference (ISSCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11408863\/11408946\/11409345.pdf?arnumber=11409345","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T19:52:44Z","timestamp":1774468364000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11409345\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,15]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isscc49663.2026.11409345","relation":{},"subject":[],"published":{"date-parts":[[2026,2,15]]}}}