{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:51:44Z","timestamp":1729623104957,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/issoc.2003.1267719","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T21:52:40Z","timestamp":1087854760000},"page":"65-68","source":"Crossref","is-referenced-by-count":0,"title":["Immediate optimization for compressed transport triggered architecture instructions"],"prefix":"10.1109","author":[{"given":"J.","family":"Heikkinen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Rantanen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Cilio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Takala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Corporaal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Microprocessor Architectures From VLIW to TTA","year":"1997","author":"corporaal","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.2247"},{"key":"ref10","first-page":"2318","article-title":"Improving dictionary-based code compression in VLIW architectures","volume":"e82 a","author":"nam","year":"1999","journal-title":"IEICE Trans Fundamentals of Electronics Commun and Comput Sciences"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IWSOC.2003.1213033"},{"key":"ref11","first-page":"66","article-title":"A code decompression architecture for VLIW processors","author":"xie","year":"2001","journal-title":"Proc 34th Annual Symp Microarchitecture"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"19","DOI":"10.3233\/ICA-1998-5103","article-title":"Using transport triggered architectures for embedded processor design","volume":"5","author":"corporaal","year":"1998","journal-title":"Integrated Computer-Aided Eng"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809446"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1002\/(SICI)1097-024X(199909)29:11<1005::AID-SPE270>3.0.CO;2-F"},{"article-title":"Automatic design of VLIW and EPIC instruction formats","year":"2000","author":"aditya","key":"ref2"},{"key":"ref9","first-page":"330","article-title":"MediaBench: A tool for evaluating and synthesizing multimedia communications systems","author":"lee","year":"1997","journal-title":"Proc 30th Ann IEEE\/ACM Int Symp Microarchitecture"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/362652.362658"}],"event":{"name":". 2003 International Symposium on System-on-Chip","acronym":"ISSOC-03","location":"Tampere, Finland"},"container-title":["Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8954\/28361\/01267719.pdf?arnumber=1267719","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,2]],"date-time":"2020-04-02T13:42:10Z","timestamp":1585834930000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1267719\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/issoc.2003.1267719","relation":{},"subject":[]}}