{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T07:06:59Z","timestamp":1725433619117},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/issoc.2004.1411147","type":"proceedings-article","created":{"date-parts":[[2005,3,31]],"date-time":"2005-03-31T13:26:51Z","timestamp":1112275611000},"page":"61-67","source":"Crossref","is-referenced-by-count":3,"title":["A low-power i-cache design with tag-comparison reuse"],"prefix":"10.1109","author":[{"given":"K.","family":"Inoue","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Tanaka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.G.","family":"Moshnyaga","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Murakami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1145\/313817.313948","article-title":"Way-predicting set-associative cache for high performance and low energy consumption","author":"inoue","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106768"},{"journal-title":"Mediabench","year":"0","key":"10"},{"key":"1","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1145\/313817.313860","article-title":"Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation","author":"ghose","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995713"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224092"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1997.568087"},{"key":"4","first-page":"143","article-title":"Analytical energy dissipation models for low power caches","author":"kamble","year":"1997","journal-title":"Proceedings of 1997 International Symposium on Low Power Electronics and Design LPE"},{"key":"9","article-title":"Low power design techniques for microprocessors","author":"segars","year":"2001","journal-title":"ISSCC Tutorial"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991105"},{"journal-title":"SimpleScalar Simulation Tools for Microprocessor and System Evaluation","year":"0","key":"11"},{"year":"0","key":"12"}],"event":{"name":"2004 International Symposium on System-on-Chip, 2004.","location":"Tampere, Finland"},"container-title":["2004 International Symposium on System-on-Chip, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9673\/30557\/01411147.pdf?arnumber=1411147","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T13:51:17Z","timestamp":1497621077000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1411147\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/issoc.2004.1411147","relation":{},"subject":[]}}