{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:21:16Z","timestamp":1725560476396},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/issoc.2004.1411160","type":"proceedings-article","created":{"date-parts":[[2005,3,31]],"date-time":"2005-03-31T13:26:51Z","timestamp":1112275611000},"page":"103-106","source":"Crossref","is-referenced-by-count":11,"title":["A reconfigurable FPU as IP component for SoCs"],"prefix":"10.1109","author":[{"given":"C.","family":"Brunelli","sequence":"first","affiliation":[]},{"given":"F.","family":"Campi","sequence":"additional","affiliation":[]},{"given":"J.","family":"Kylliainen","sequence":"additional","affiliation":[]},{"given":"J.","family":"Nurmi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","first-page":"355","article-title":"Proteo: A new approach to network-on-chip","author":"tortosa","year":"2002","journal-title":"Proc of the International Conference on Systems and Networks Communication"},{"journal-title":"A Standard for Binary Floating-Point Arithmetic","year":"0","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2003.1267734"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IWRSP.2000.855216"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2001.952995"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1998.722994"},{"key":"10","article-title":"Lower SoC operating frequencies to cut power dissipation","author":"leibson","year":"2004","journal-title":"Portable Design"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234288"},{"key":"6","first-page":"456","article-title":"Ip-reusable 32-bit vliw rise core","author":"campi","year":"2001","journal-title":"the 25th European Solid-State Circuits Conference"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2003.1267707"},{"key":"4","first-page":"104","article-title":"Cost\/performance trade-off in floating-point unit design for 3D geometry processor","author":"jeong","year":"0","journal-title":"AP-ASIC 1999"},{"key":"9","article-title":"ARM adds floating-point unit to processor cores","author":"clarke","year":"2001","journal-title":"EE Times"},{"key":"8","doi-asserted-by":"crossref","DOI":"10.1145\/502217.502232","article-title":"A software development tool chain for a reconfigurable processor","author":"rosa","year":"2001","journal-title":"Proc Int Conf Compilers Architectures and Synthesis Embedded Systems"}],"event":{"name":"2004 International Symposium on System-on-Chip, 2004.","location":"Tampere, Finland"},"container-title":["2004 International Symposium on System-on-Chip, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9673\/30557\/01411160.pdf?arnumber=1411160","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T13:51:17Z","timestamp":1497621077000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1411160\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/issoc.2004.1411160","relation":{},"subject":[]}}