{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T14:12:44Z","timestamp":1725545564998},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/issoc.2004.1411161","type":"proceedings-article","created":{"date-parts":[[2005,3,31]],"date-time":"2005-03-31T18:26:51Z","timestamp":1112293611000},"page":"107-110","source":"Crossref","is-referenced-by-count":1,"title":["Verification of a 32-bit RISC processor core"],"prefix":"10.1109","author":[{"given":"T.","family":"Kasanko","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Nurmi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/296333.296345"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.782236"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378475"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/307988.307989"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2003.1267707"}],"event":{"name":"2004 International Symposium on System-on-Chip, 2004.","location":"Tampere, Finland"},"container-title":["2004 International Symposium on System-on-Chip, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9673\/30557\/01411161.pdf?arnumber=1411161","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T04:01:56Z","timestamp":1489550516000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1411161\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/issoc.2004.1411161","relation":{},"subject":[]}}