{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T11:46:54Z","timestamp":1725623214065},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/issoc.2013.6675263","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T16:20:55Z","timestamp":1386174055000},"page":"1-8","source":"Crossref","is-referenced-by-count":6,"title":["A cycle accurate simulation framework for asynchronous NoC design"],"prefix":"10.1109","author":[{"given":"Federico","family":"Terraneo","sequence":"first","affiliation":[]},{"given":"Davide","family":"Zoni","sequence":"additional","affiliation":[]},{"given":"William","family":"Fornaciari","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"22","first-page":"3","article-title":"Mibench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Proceedings of the Workload Characterization 2001"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.22"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492732"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333721"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2011.5762734"},{"key":"12","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2063384.2063454","article-title":"Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation","author":"carlson","year":"2011","journal-title":"High Peiformance Computing Networking Storage and Analysis (SC) 2011 International Conference for"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2011.6089221"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"2","article-title":"Networks for multi-core chips: A contrarian view","author":"borkar","year":"2007","journal-title":"Special Session at ISLPED"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.6"},{"key":"10","first-page":"134","article-title":"Polaris: A system-level road map for on-chip interconnection networks","author":"soteriou","year":"2006","journal-title":"ICCD 2006"},{"key":"7","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1109\/NOCS.2007.14","article-title":"Bi-synchronous fifo for synchronous circuit communication well suited for network-on-chip in gals architectures","author":"miro panades","year":"2007","journal-title":"Networks-on-Chip 2007 NOCS 2007 First International Symposium on"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/NANONET.2006.346219"},{"key":"5","doi-asserted-by":"crossref","first-page":"110","DOI":"10.1145\/1278480.1278509","article-title":"voltage-frequency island partitioning for gals-based networks-on-chip","author":"ogras","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICTEL.2010.5478830"},{"year":"2005","author":"renau","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2008.4492732"}],"event":{"name":"2013 International Symposium on System-on-Chip (SoC)","start":{"date-parts":[[2013,10,23]]},"location":"Tampere, Finland","end":{"date-parts":[[2013,10,24]]}},"container-title":["2013 International Symposium on System on Chip (SoC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6663741\/6675254\/06675263.pdf?arnumber=6675263","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,4]],"date-time":"2019-08-04T08:23:42Z","timestamp":1564907022000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6675263\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/issoc.2013.6675263","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}