{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:04:31Z","timestamp":1729616671428,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/isvdat.2014.6881060","type":"proceedings-article","created":{"date-parts":[[2014,8,22]],"date-time":"2014-08-22T16:38:16Z","timestamp":1408725496000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["An FPGA implementation of image signature based visual-saliency detection"],"prefix":"10.1109","author":[{"given":"Bhavit","family":"Kaushik","sequence":"first","affiliation":[]},{"given":"Ravi","family":"Saini","sequence":"additional","affiliation":[]},{"given":"Anil","family":"Saini","sequence":"additional","affiliation":[]},{"given":"Sanjay","family":"Singh","sequence":"additional","affiliation":[]},{"given":"A. S.","family":"Mandal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1364\/JOSAA.23.002462"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1016\/0010-0285(80)90005-5"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1049\/iet-wss.2011.0038"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1978.1094144"},{"key":"18","first-page":"281297","article-title":"The Relationship between information prioritization and Visual Distinctness in Two Progressive Image Transmission Schemes","volume":"37","author":"rodriguez et ai","year":"2004","journal-title":"Pattern Recognition"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/76.486423"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/CISS.2011.5766191"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.41"},{"key":"13","article-title":"Optimizing the FPGA Memory Design for a Sobel Edge Detector","author":"moore","year":"2009","journal-title":"ERSA"},{"key":"14","first-page":"1","article-title":"FPGA-Accelerated preattentive segmentation in primary visual cortex","author":"bouganis","year":"2006","journal-title":"FPL"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2005.862755"},{"key":"12","doi-asserted-by":"crossref","DOI":"10.1117\/12.469519","article-title":"Real-time high performance attention focusing in outdoors color video streams","author":"itti","year":"2002","journal-title":"Proceedings of SPIE Conference Human Vision and Electronic Imaging"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.1997.651734"},{"key":"3","article-title":"Graph-based visual saliency","author":"harel","year":"2006","journal-title":"NIPS"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/1870076.1870080"},{"key":"2","first-page":"219","article-title":"Shifts in selective visual attention: Towards the underlying neural circuitry","volume":"4","author":"koch","year":"1985","journal-title":"Human Neurobiology"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/34.730558"},{"key":"10","article-title":"Image Signature: Highlighting sparse salient regions","volume":"34","author":"hou","year":"2012","journal-title":"IEEE Transactions on Pattern Analysis and Machine Intelligence"},{"key":"7","article-title":"State-of-the-art in visual attention modeling","author":"borji","year":"2012","journal-title":"IEEE Transactions on Pattern Analysis and Machine Intelligence"},{"key":"6","article-title":"A novel multiresolution spatiotemporal saliency detection model and its applications in image and video compression","author":"guo","year":"2010","journal-title":"IEEE Trans on Image Processing"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2009.5413815"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2009.5459467"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763198"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1016\/S1077-2014(03)00036-6"}],"event":{"name":"2014 18th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2014,7,16]]},"location":"Coimbatore, India","end":{"date-parts":[[2014,7,18]]}},"container-title":["18th International Symposium on VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6873898\/6881034\/06881060.pdf?arnumber=6881060","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T19:12:52Z","timestamp":1498158772000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6881060\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2014.6881060","relation":{},"subject":[],"published":{"date-parts":[[2014,7]]}}}