{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T12:06:58Z","timestamp":1725797218642},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/isvdat.2015.7208052","type":"proceedings-article","created":{"date-parts":[[2015,8,20]],"date-time":"2015-08-20T17:53:11Z","timestamp":1440093191000},"page":"1-9","source":"Crossref","is-referenced-by-count":3,"title":["Case study: Re-visiting SoC verification challenges and best practices"],"prefix":"10.1109","author":[{"given":"Prokash","family":"Ghosh","sequence":"first","affiliation":[]},{"given":"Sandip","family":"Ghosh","sequence":"additional","affiliation":[]},{"given":"Pritpal","family":"Singh","sequence":"additional","affiliation":[]},{"given":"Saurabh","family":"Mishra","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"VCS Xprop and VCS from Synopsys Inc","year":"0","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2013.37"},{"journal-title":"Freescale B4860 SoC description and documentation","year":"0","key":"ref12"},{"journal-title":"Cadence IFV tool","year":"0","key":"ref13"},{"journal-title":"Denali memory models for flash memory device or DDR4 memory device are available","year":"0","key":"ref14"},{"journal-title":"DDR4 specification","year":"0","key":"ref15"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629968"},{"key":"ref3","first-page":"52","article-title":"Challenges in System on Chip Verification","author":"noah","year":"0","journal-title":"Microprocessor Test and Verification 2006 MTV '06"},{"article-title":"System On A Chip Verification: Methodology and Techniques","year":"2002","author":"rashinkar","key":"ref6"},{"key":"ref5","article-title":"Verification of the CoreNet Fabric with System Verilog","author":"page","year":"2009","journal-title":"Proc of IEEE International Workshop on Microprocessor Test and Verification (MTV)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2013.6863985"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2006.319974"},{"journal-title":"T1024 product description Documentation & reference manual","year":"0","key":"ref2"},{"journal-title":"T1024 product description Documentation & reference manual","year":"0","key":"ref1"},{"article-title":"Pin Muxing Verification using Formal Analysis","year":"0","author":"gupta","key":"ref9"}],"event":{"name":"2015 19th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2015,6,26]]},"location":"Ahmedabad, India","end":{"date-parts":[[2015,6,29]]}},"container-title":["2015 19th International Symposium on VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7166536\/7208044\/07208052.pdf?arnumber=7208052","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T17:54:44Z","timestamp":1490378084000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208052\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2015.7208052","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}